3.1 CDN-SET-Induced Incorrect Latching in a Single Sequential Element

The circuits shown in Fig. 3 are used for comparative study of the incorrect data latching caused by SET on the clock signal in a single sequential element. In the simulations of the circuits shown in Fig. 3, I_peak was set to 1 mA.

Fig. 3.Full-screen View

(Color online) Circuits used for comparative study of the CDN-SET-induced incorrect latching in a single sequential element.

As shown in the figures, in the simulations, an SET was injected in copy 1 and the signals in copy 2 could be treated as reference signals. As shown in Fig. 3(a), two clock signals in the two copies (CK1_DFF and CK2_DFF) were connected to two inputs of one XOR cell. From the output ZXOR_CK_DFF of this XOR cell, we could determine whether there was an effective SET occurring on CK1_DFF and the pulse width of the effective SET. Similarly, the outputs of the two copies (Q1_DFF and Q2_DFF) were connected to two inputs of another XOR cell. From the output ZXOR_Q_DFF of this XOR cell, we could determine whether CDN-SET-induced incorrect data latching occurred and how long it lasted. The circuit shown in Fig. 3(b), which is used for simulations of the D-latch, is similar to that in Fig. 3(a).

In the simulations, the clock input CK in Fig. 3(a) and Fig. 3(b) were stimulated by one clock signal. The data inputs D in the two circuits were also stimulated by one data signal. Both the clock signal and data signal changed periodically. Considering that the clock signal usually operates at the highest speed, we set the data cycle to double of the clock cycle.

3.2 Comparative Study in a Case Circuit

Based on the dynamic analysis method in [17, 21], we evaluated the SET susceptibility of the CDN in a DFF-based design and in an optimized design of a case circuit. The two designs were identical except for the type of the sequential elements. This can make the comparative study result more accurate. By analyzing the function and timing behavior of each flip-flop, we replaced some positive-edge-triggered flip-flops in the case circuit with active-low D-latches in the optimized design according to [15]. In the simulations, both designs worked in real time, the injection location of the SET traversed all clock nodes on the CDN, the injection time of the SET was random, and the SET pulse width was random within a certain range. The IC operation in the real radiation environment might be hindered by radiation particles at any position and at any time. The pulse width of the SET occurrence varies with the type of the radiation particles, supply voltage, temperature, angle of incidence, and so on. Therefore, our simulations could more realistically reflect the IC operation after radiation in the aerospace, and therefore could make the obtained information more truthful and accurate.

The DFF-based design of a case circuit was implemented first by Encounter from Candence using 65-nm bulk complimentary metal-oxide semi-conductor (CMOS) technology. Then, the DFFs that could be replaced by D-latch were replaced by D-latches with similar drive capabilities. Because the area of the D-latch is less than that of the DFF with similar drive capability, the replacement would not introduce violation or short in the design. In this way, we could get the optimized design, which was exactly the same with the DFF-based design.

For the sake of higher simulation accuracy, the files including the detailed standard parasitic format (DSPF) files of all designs were extracted and used for simulations. According to [17], two selfsame copies of the DSPF file of the DFF-based (optimized) design were included in one HSPICE netlist. As shown in Fig. 4, two duplicates of the output Q of the same sequential element were connected respectively to the two inputs of one XOR cell (Q_XOR1 to Q_XORn) to study the CDN-SET-induced incorrect latching in each sequential element. The "n" in "Q_XORn" is the total number of sequential elements connected to the clock leaf nodes in the case circuit.

Fig. 4.Full-screen View

(Color online) Dynamic SET sensitivity analysis method for CDN.

In each simulation, the same inputs of the two copies were stimulated by one signal, and an SET was injected at one clock node in copy 1. Because there was no SET injection in the other copy, its signals could be treated as reference signals. If the SET propagating to the leaf clock nodes induced an incorrect data latching in the receiving sequential element, a pulse would appear at the output of the corresponding XOR cell. The duration of the pulse represented the duration of incorrect latching.

In the simulations of the case circuit, I_peak was set to 725 μA. The simulations were controlled by a shell script. All the simulations traversing all clock nodes on the CDN could be implemented automatically by running the script. Even if the simulations were interrupted for some reason, we could restart the simulations by modifying the node list. Information, such as the name of the sequential element with CDN-SET-induced incorrect latching and the duration of the incorrect latching, would be recorded. By comparing the numbers and durations of incorrect latching in the DFF-based design and optimized design, we can obtain the relative SET susceptibility of the CDN in each design.

3.3 Heavy Ion Irradiation Experiment Setup

To further investigate the influence of the type of the sequential element on the SET susceptibility of the CDN, we designed a test chip in 130-nm bulk CMOS technology. This test chip was fabricated at Semiconductor Manufacturing International Corporation (SMIC). This test chip includes eight test chains. Four of the chains, which were numbered 1, 3, 5, and 7, are used for the comparative study. The constructions of these four chains are shown in Table 1 and Fig. 5.

Fig. 5.Full-screen View

Schematic of the four test chains used for the comparative study.

The test chains were designed by referring to the shift register with latches in [14] and that with flip-flops in [22]. The differences between the four test chains are in terms of the presence of SET target (combinational logic element at the data input of the sequential element) and the kind of sequential element that is adopted. For the first chain (Number 1 in Table 1 shown in Fig. 5(a)), which is referred to as SETtarget_Latch_chain, there are buffers at the data inputs of the D-latches. For the second chain (Number 3 in Table 1 shown in Fig. 5(b)), which is referred to as SETtarget_DFF_chain, there are buffers at the data inputs of the DFFs. For the third and fourth chains (Number 5 and 7 in Table 1 shown in Fig. 5(c) and Fig. 5(d)), respectively, which are referred to as Latch_chain and DFF_chain in the test chip, there is no combinational logic at the data inputs of the D-latches and DFFs.

In the four test chains, all sequential elements were hardened by the dual interlocked storage cell (DICE) [23] technique. All data inputs of the sequential elements were hardened by the time redundancy technique [24, 25]. In this way, we were able to rule out the influence of single-event upsets (SEUs) in the sequential elements and the incorrect data latching caused by SETs on the data signals. In the heavy ion irradiation experiments, the test approach proposed in [22] was adopted to rule out the influence of the SEUs in the sequential elements and the incorrect data latching caused by SETs on the data signals.

4.1 Simulation Results of the Single Sequential Element

The simulations were performed on the DFF and D-latch with 130-nm CMOS technology. As shown in Fig. 3(a) and Fig. 3(b), in each simulation, an SET was injected at the output of one clock inverter in one copy. The injection time of the SETs was random in the range less than 1000 ps. This range was set by referring to the work in [26]. In each simulation, the appearance of the pulse at the signal XOR_Q_DFF (XOR_Q_Latch) and its effective pulse width were recorded. We can obtain the duration of incorrect data latching according to the effective pulse width. Two thousand simulations (1000 P-hit simulations and 1000 N-hit simulations) were performed respectively on the DFF and D-latch.

The total number of CDN-SET-induced incorrect data latching for DFF and D-latch are shown in Fig. 6. As shown in the figure, in the 2000 simulations, the CDN-SET-induced incorrect data latching occurred 246 times in the active-low D-latch. However, the total number of CDN-SET-induced incorrect latching in DFF reached up to 698. This means that, compared with D-latch, DFF is more sensitive to SETs on the clock signal, especially in the P-hit instance. This was mainly because of a 0-to-1 upset that occurred on the clock signal in the P-hit instance, which is opaque for the active-low D-latch when the clock is high. Unless the P-hit-induced SET happens to occur at or near the falling edge of the clock signal, which will cause the falling edge to lag behind its expected falling transition time, and the data input of the D-Latch is different from its stored state, the P-hit-induced SET will cause the time to start latching slightly behind the expected time in the D-Latch.

Fig. 6.Full-screen View

(Color online) Total number of incorrect data latching in the simulations for the DFF and D-latch.

In the N-hit instance, when radiation-induced clock race occurs or radiation-induced clock jitter causes the falling transition time of the clock signal to be earlier than the expected time, and the data input of the D-Latch is different from its stored state, an incorrect latching will occur in D-Latch. However, when an incorrect data latching occurred in D-latch, an incorrect latching also usually occurred in DFF simultaneously, and duration of the CDN-SET-induced incorrect latching in DFF was usually much longer than that in D-latch, as listed in Table 2. This is consistent with the analysis in Sec. 2. The duration of the CDN-SET-induced incorrect latching in D-latch is usually less than that in DFF. Moreover, a shorter incorrect latching is less likely to cause incorrect latching in the receiving sequential elements. Therefore, the CDN-SET-induced incorrect latching detected in the receiving sequential elements behind a D-latch will be smaller than that detected in the receiving sequential elements behind a DFF.

4.2 Comparative Study Results of the Case Circuit

Two designs of a case circuit were implemented with the 65-nm bulk CMOS technology. Function verification of the two designs was made before the simulations to ensure correct operation of the designs. As mentioned above, the case circuit worked in real time in the simulations. Six sets of traversal simulations were performed on each design. This can make the simulation results more statistical and convictive. In each set of simulations, the SET injection location traversed the 97 clock nodes on the CDN of the case circuit. The pulse width and injection time of the SET were random. The random pulse width of the injected SET was less than 500 ps, which was entirely set by referring to the previous work [27] of our group.

Fig. 7 shows the number of incorrect data latching in each sequential element caused by SETs on the CDN in the 1164 (2∗(97×6)) simulations. The DFFs and D-latches in which incorrect data latching did not occur are not shown. As shown in the figure, in the 1164 simulations, the CDN-SET-induced incorrect latching occurred 168 times in the DFF-based design and 37 times in the optimized design.

Fig. 7.Full-screen View

(Color online) Number of CDN-SET-induced incorrect data latching in the DFF-based design and optimized design.

As described in Sec. 4.1, the duration of the CDN-SET-induced incorrect latching in D-latch is usually much less than that in DFF, and a shorter incorrect latching is less likely to cause incorrect latching in the receiving sequential elements. Thus, compared with the simulation results of the single sequential element in Sec. 4.1, the CDN-SET-induced incorrect latching detected in the sequential elements in the optimized design were smaller than those detected in the DFF-based design. These results also showed that SETs on the CDN were more likely to cause incorrect data latching in the DFF-based design than in the optimized design. That is to say, the DFF-based design is more sensitive to SETs on the CDN than the optimized design.

4.3 Heavy Ion Irradiation Experiment Results

Heavy ion broad-beam experiments were performed on the test chip described in Sec. 3.3. The layout and die micrograph of the test chip are shown in Fig. 8. The cross sections of each test chain were measured in three test modes for the ions of Bismuth (Bi), Germanium (Ge), and Chlorine (Cl) at normal incidence. The heavy ion experiment for Bi was performed at the Heavy Ion Research Facility in Lanzhou (HIRFL), China, and the experiments for Ge and Cl were performed at the HI-13 Tandem Accelerator in China Institute of Atomic Energy in Beijing.

Fig. 8.Full-screen View

(a) (Color online) Layout and (b) die micrograph of the test chip.

It may be recalled from Sec. 3.3 that all the sequential elements and their data inputs in the four test chains were hardened by design to rule out the influence of SEUs that may occur in the sequential elements and incorrect data latching caused by SETs on the data signals. To fully eliminate this influence, we considered the test modes 00 and 11 in which the data patterns were a constant value of 0 and 1, respectively. Because the data pattern is static in these two test modes, the SETs on the CDN will not induce incorrect data latching of the sequential elements. Because there was no SET target in the chains 5 and 7, all upsets detected in the test modes 00 and 11 were SEUs initiated in the sequential elements. For the test chains 1 and 3, which had SET targets, the total cross sections detected in the test modes 00 and 11 gave us the cross sections for the SET targets and sequential elements together without the influence of the CDN. We could obtain the contribution of the SET targets alone by subtracting the DFF (D-latch) cross section component measured in chain 7 (5) from the total cross sections of chain 3 (1). In the test mode 01, a "010101" pattern was clocked into the devices. For the test chains 1 and 3, the total cross sections measured were the sum of the sequential element, clock, and SET target components. For the test chains 5 and 7, the total cross sections measured were the sum of the sequential element and the clock components. By subtracting the sequential element and SET target components, we could obtain the upsets caused by SETs on the CDN.

Cross sections of the four test chains experimentally measured are shown in Fig. 9. The data were collected using Bi with LET of 99.8 MeV-cm²/mg, Ge with LET of 37.6 MeV-cm²/mg, and Cl with LET of 15.2 MeV-cm²/mg. In the experiments for Ge and Cl, the total fluence of the beams used in the experiments was 1×10⁷ ions/cm². In the experiment for Bi, the fluence was 5×10⁶ ions/cm² due to test time constraint. As shown in the figure, in the test modes 00 and 11, the cross sections of all the four test chains were 0. This was mainly because all sequential elements and all their data inputs were hardened by design. This meant that, in our experiments, the SET targets and sequential elements had no contribution to the cross sections and the cross sections measured in the test mode 01 were the contribution of the CDN.

Fig. 9.Full-screen View

(Color online) Cross sections for the four test chains experimentally measured at normal incidence. In test modes 00 and 11, the data pattern was a constant value of 0 and 1, respectively. In test mode 01, a "010101" pattern was clocked into the devices.

As mentioned in Sec. 4.1, D-latch is much less sensitive to P-hit-induced SET on the clock signal. Moreover, a previous study revealed that the effective sensitive area of PMOS is much larger than that of NMOS [28], and thus 0-to-1 upsets are more likely to occur than 1-to-0 upsets [29]. Therefore, the CDN-SET-induced incorrect latching in D-latch-based chains detected in the heavy ion experiments was further reduced. According to the experimental results in test mode 01, the SEU cross sections induced by SETs on the CDN in the experiments for Bi were 7.5 μm²/bit and 3 μm²/bit in the test chain 3 (SETtarget_DFF_chain) and test chain 7 (DFF_chain), respectively. In addition, these two cross sections respectively were 0.625 μm²/bit and 1 μm²/bit in the experiments for Ge. However, no upset was detected in the D-latch-based test chains (chains 1 and 5), i.e., the SEU cross sections induced by SETs on the CDN were 0 in the D-latch-based test chains. This means that, compared with the D-latch-based test chains, the DFF-based chains were much more sensitive to SETs on the CDN. The same conclusion can be drawn from the experimental results for Cl, although the cross section measured was small due to low LET of Cl. This further verifies that, compared with the D-latch-based design, the DFF-based design is more sensitive to SETs on the CDN.