SDD detector

Silicon X-ray detectors are widely used in space applications, including silicon drift detectors (SDDs) [15-18], silicon photomultipliers [19, 20], silicon microstrips [21, 22], Si-PIN detectors [23, 24], CCD detectors [25, 26], and APS CMOS imaging sensors [27]. A 500 μm thick SDD is selected as the X-ray sensor. Its unique electrode structure provides an ultralow capacitance, enabling operation at a short peaking time, which increases the count rate. The energy resolution is further improved using a thermoelectric cooler (TEC). The SDD, along with a CMOS charge-sensitive preamplifier, is mounted on the TEC. The detector is positioned behind a thin window composed of a 150 nm silicon nitride film covered with 250 nm aluminum. The two XDMs use the same type of SDD; however, the aperture areas restricted by the collimator are 0.17 cm² and 0.005 cm², respectively. A passive graded shield surrounding the detector package protects the detector against space background radiation and fluorescent photons from surrounding materials. Additionally, two ²⁴¹Am radioactive sources are mounted between the detector plane and collimator in both SXDUs for in-flight calibration and self-verification.

When detector leakage current accumulates in the preamplifier, the ramp output eventually saturates. A reset pulse is applied to restore the detector anode to ground potential, as shown in Fig. 2. The large transient caused by the reset pulse can interfere with signal processing; therefore a window of 10 μs is implemented to eliminate its effects.

Fig. 2Full-screen View

(Color online) A pulse resets the ramp when saturation is reached

TEC characteristics

The detector leakage current is sensitive to the operating temperature, doubling for every 7 ℃ increase, as described by [28] $I_0=T^2{e}^{-E_{\text{g}}/2kT},$ (1) where I₀ is the leakage current, T is the detector operating temperature, E_g is the silicon bandgap energy (which is temperature-dependent), and k is the Boltzmann constant. The TEC reduces electronic noise in the detector and preamplifier. The heat extracted by the TEC is dissipated through a mounting stud attached to a copper heat radiator. Figure 3 shows the TEC voltage and current at a room temperature of +25 ℃. The SDD temperature decreases exponentially as TEC power increases, allowing the silicon detector to be cooled to -30 ℃. Since the leakage current of the SDD increases after radiation exposure [29-32], the TEC temperature can be adjusted using a command. Additionally, the TEC can be turned off if necessary. The voltage and current of the TEC driver are recorded every second.

Fig. 3Full-screen View

Exponential temperature drop with TEC power

Preamplifier reset rate

The preamplifier periodically resets the charge accumulated on the feedback capacitance due to X-ray signals and leakage current: $I_0=C_{\text{f}}{V}_{\text{ramp}}{f}_{\text{reset}},$ (2) where I₀ is the leakage current, C_f is the preamplifier feedback capacitance (typically 25 fF), V_ramp is the ramp voltage, and f_reset is the ramp-reset rate. The reset rate decreases exponentially with decreasing detector temperature and stabilizes at a nominal value of 12-13 Hz in the absence of incident radiation. However, it increases with higher incidence rates and deposited energy. To monitor variations in SDD leakage current during radiation exposure, the reset rate is recorded every second.

SDD and TEC drivers

The preamplifier driver circuit generates and filters power, sends reset signals to the preamplifier, and buffers and amplifies the preamplifier output to drive the front-end electronics.

The TEC driver reads the temperature diodes inside the SDD package and supplies power to the TEC. The temperature diode is biased using a 160 μA current source. A proportional-integral-derivative (PID) control feedback loop maintains the SDD at the desired temperature, which is set via a digital-to-analog converter (DAC). The TEC power is supplied by a high-efficiency DC-DC converter, with output ripple minimized using an LC-type filter. The voltage and current of the TEC driver, along with the set and measured temperatures, are converted using an ADC. These parameters, together with the ramp-reset rate, are used to assess the operational status of the SDD in orbit.

Shaping amplifier

The preamplifier generates a ramp output composed of small steps. Its output is differentiated to measure the step voltage. The shaping amplifier, designed using two-pole multiple-feedback active low-pass filters [33], as shown in Fig. 5, enhances the signal-to-noise ratio. The amplifiers are optimized to achieve a Bessel phase response, ensuring a constant group delay within the passband. The step response exhibits no overshoot or ringing, which is essential for the performance of the spectrometer. While the rising edge of the shaping output is steep, the voltage decays exponentially back to the baseline. These exponential tails extend many times the duration of the full width at half maximum (FWHM). Pulses that overlap during the extended window pile-up, particularly at high count rates. Reducing the FWHM mitigates pulse pile-up but introduces additional noise.

Fig. 5Full-screen View

Shaping amplifier circuit

Two parallel shaping amplifiers with different time constants are designed to serve distinct purposes. The first amplifier is optimized for better timing accuracy, while the second is designed to achieve higher spectral resolution. The shaping amplifiers, with peaking times of 315 ns and 65 ns, are referred to as “slow shaping” and “fast shaping”, respectively. The fast-shaping channel is optimized to improve double-pulse resolution and reduce pile-up; however, it introduces more noise. Consequently, a higher threshold—set by a DAC—is required. In contrast, the slow-shaping channel uses a longer peaking time to extract spectral information. When the amplitude of the slow-shaping channel exceeds the threshold, the peak value is held by the peak holder and digitized by an ADC.

Table 2 lists the design parameters of the slow-shaping channel. The group delay is simulated to be constant in the passband at 853.8 ns, as shown in Fig. 6.

Fig. 6Full-screen View

Group delay simulation of the slow-shaping amplifier

A pulse generator is connected to the input of the shaping amplifier to simulate the X-ray events. Figure 7 shows the transient response of the slow channel, revealing no overshoot and no ring. The rise time of the slow-shaping amplifier is measured to be 315 ns, the fall time is 945 ns, and the pulse width is less than 2.8 μs.

Fig. 7Full-screen View

(Color online) Oscilloscope traces showing the slow-shaping amplifier and differential signals

Traditional pile-up detection is performed using a fast/slow-channel approach [34]. It cannot distinguish pulses that overlap in the fast channel. The differential of the shaping amplifier generates a bipolar output. As Fig. 8 shows, the pulse width of the differential signal is significantly smaller than that of the shaping amplifier. Therefore, the differential signals of the fast channel are selected for pile-up rejection.

Fig. 8Full-screen View

(Color online) Oscilloscope traces showing the fast-shaping amplifier and differential signals

The time interval of an X-ray photon can be described by an exponential distribution. $f(\tau )=\lambda e^{-\lambda \tau }$ (3) where τ is the dead time and λ is the average incoming rate, which is assumed to be 1×10⁵ counts·s^-1. The dead time caused by the shaping amplifier is 2.8 μs for the slow channel. The probability of a non-paralyzable pile-up can be calculated as $P(X\le \tau )=\frac{\lambda \tau }{1+\lambda \tau }.$ (4) For a slow channel, τ= 2.8 μs, the probability is 21.9%. The probability is reduced to 4.8% for a fast channel with a dead time of 0.5 μs. The throughput is significantly better, making it suitable for calculating the true input rate.

Peak-hold circuit

The rise time of the SDD output is a function of the incident position [35]. The peaking time of the slow channel is significantly longer than the variation in the rise time, with a maximum of 30 ns. Therefore, the amplitude of the slow-channel amplitude does not depend on the event position. The flat-top duration of the fast channel is shorter than the rise time, leading to pulse height loss due to the ballistic deficit. As a result, events originating far from the center could be rejected by comparing the fast and slow amplitudes. Both peak values are sampled for space-background rejection.

The diagram of the peak-hold circuit is shown in Fig. 9. A CMOS analog switch is inserted between the shaping amplifier and the hold-capacitor stage. When a pulse peak is detected, the peak value is held in the capacitor by turning off the switch until it is read out by a 16-bit ADC. Only the 12 most significant bits are stored. The charge on the capacitor is reset by turning on the switch. The peak value from the capacitor is buffered by a unit-gain operational amplifier with a low input-bias current. Additionally, low-leakage, low-dielectric absorption capacitors are essential. The peak value of the fast-shaping amplitude is obtained in the same manner, with both the fast and slow peak-hold circuits sharing a common ADC. Figure 10 shows the input waveform of the ADC. A CMOS analog switch is used to select a single channel. The switch features an extremely high switching speed and ensures break-before-make switching. The charge injection is less than 2 pC, which is crucial for high-precision peak-height capture.

Fig. 9Full-screen View

Peak-hold circuit and multiplexing of two channels

Fig. 10Full-screen View

(Color online) Waveform of the input and conversion pin of the peak-height ADC

Figure 11 shows the timing of the switches in the peak-hold circuit. The durations of the peak-hold signals “PH_F” and “PH_S” for the fast and slow channels are 150 ns and 200 ns, respectively. The ADC starts the conversion signal, “CNV”, for the two channels with delays of 100 ns and 150 ns, respectively. At the end of each peak-hold signal, the switch changes its state. It is important to note that, in some cases, “PH_F” may be absent, as the fast channel threshold is higher. As a result, the assertion of “PH_MUX” is controlled by both “HOLD_S” and “PH_F.” Here, “HOLD_S” is the “HOLD” signal of the slow channel, while “HOLD_F” corresponds to that of the fast channel. At the rising edge of “HOLD_S”, if “PH_F” is high, then “PH_MUX” is asserted at the falling edge of “PH_F”; otherwise, “PH_MUX” is asserted immediately.

Fig. 11Full-screen View

Timing of the switches in the peak-hold circuit

The “HOLD” signal is generated by connecting the differentiating amplifier output to a comparator with hysteresis. “HOLD_S” and “HOLD_F” are generated in the same approach, as shown in Fig. 12 and 13. The comparator U₂ output, known as “HOLD,”, switches to high for input voltages greater than V_HI and does not switch to low until the input voltage is less than V_LO (i.e., at the zero crossing). $V_{\text{HI}}=\left(VCC-1\right)\frac{R_1}{R_1+R_2}$ (5) $V_{\text{LOW}}=0$ (6) where VCC = 5 V, R₁ = 100 Ω, R₂ = 10 kΩ, and V_HI = 40 mV. The latch pin of U₂ is connected to the output of U₁. Therefore, the “HOLD” remains at a low state unless the shaping-amplifier amplitude exceeds the threshold.

Fig. 12Full-screen View

Trigger logic circuit

Fig. 13Full-screen View

Timing of trigger logic

Pile-up rejection

If the two pulses are too close in time, the height of the second pulse can be affected. Errors in the measured pulse height may distort the spectrum. The overlapping pulse in the slow channel was identified using the differential signal of the fast channel, as described earlier. To obtain a clean spectrum, all overlapping pulses are rejected. The analog shaper exhibits an infinite impulse response. Even when the tail drops rapidly toward the baseline, a small contribution remains [36]. The dead-time window widths, “WINDOW_S” and “WINDOW_F”, for the slow and fast channels, are 2.8 μs and 0.5 μs, respectively, as shown in Fig. 14. If an event occurs during the dead time, the dead time is extended, which reduces throughput. Therefore, the dead time can be described using a paralyzable model, as shown in Fig. 15 [37].

Fig. 14Full-screen View

Timing of pile-up rejection

Fig. 15Full-screen View

(Color online) Paralyzable dead-time model

The fraction without loss is $P(X>\lambda )=e^{-\lambda \tau }.$ (7) In other words, the probabilities of count loss are 75.6% and 95.1% for the slow and fast channels, respectively. The probability of count loss is significantly higher than that of the shaping amplifier, primarily due to the dead-time window. To accurately estimate the input count rate, the “HOLD” signal of the fast channel is counted every second.