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Clock synchronization design and evaluation for trigger-less data acquisition system

NUCLEAR ELECTRONICS AND INSTRUMENTATION

Clock synchronization design and evaluation for trigger-less data acquisition system

SHANG Linfeng
SONG Kezhu
CAO Ping
Nuclear Science and TechniquesVol.23, No.6pp.361-368Published in print 20 Dec 2012
33200

For modern particle physics experiments, trigger-less data acquisition (DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility. In such new DAQ systems, global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock. In this paper, a novel synchronized clock distribution method is proposed. With the help of modulation technique, master clock module distributes system clock to each slave module. To synchronize slave clocks, the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically. Furthermore, an ADC- based method is proposed to evaluate the performance of multi-module clock synchronization simultaneously. The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range. The proposed method is simple and flexible, and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.

Trigger-less DAQ systemClock distributionSynchronizationADC-based evaluation
References
[1] Essel H G. IEEE Trans Nucl Sci, 2006, 53: 677-681.
[2] Liu Z A, Gong W X, Guo Y N, et al. RTC, 2007, 4382859: Trigger system of BESIII, RTC, Fermilab, Batavia IL, USA, April 29-May 4, 2007, 1-4.
[3] Konorov I, Angerer H, Mann A, et al. NSSMIC. 2009. 5402171: SODA: Time distribution system for the PANDA experiment, NSSMIC, Orlando, FL, USA, 2009, 1863-1865.
[4] Alessio F, Guzik Z, Jacobsson R. RTC.2009.5321838: A 40 MHz trigger-free readout architecture for the LHCb experiment, RTC, Beijing, China, May, 2009, 206-213.
[5] An Q, Bai Y X, Bi X J, et al. Nucl Instrum Meth Phys Res A, 2011, 644: 11-17.
[6] Moreira P, Serrano J, Wlostowski T, et al. ISPCS. 2009. 5340196: White Rabbit: Sub-nanosecond timing distribution over ethernet, ISPCS, Brescia, Italy, October 2009, 1-5.
[7] Li C, Liu S B, Shang L F, et al. Nucl Sci Tech, 2012, 23: 230-236.
[8] Korhonen T. Paul Scherrer Institut, Switzerland. Review of accelerator timing systems, ICALEPCS. Trieste, Italy, October, 1999, 167-170.
[9] Li H, Liu S B, Feng C Q, et al. IEEE Trans Nucl Sci, 2006, 57: 442-445.
[10]

IEEE Standard for a Precision clock synchronization protocol for networked measurement and control systems

, IEEE Std 1588-2002, IEEE Instrumentation & Measurement Society, 2002, 1-144.
Baidu ScholarGoogle Scholar
[11] Serrano J, Alvarez P, Cattin M, et al.

CERN-ATS-2009-096: The White Rabbit project

, ICALEPCS, Kobe, Japan, October, 2009.
Baidu ScholarGoogle Scholar
[12] Ding K, Zhong S C. Acta Elec Sinica, 2003, 31: 142-145.
[13] Qi G Q, Jia X L. Acta Elec Sinica, 2001, 29: 1164-1167.
[14] Cao Z, Liu S B, Li C, et al. Nucl Sci Tech, 2011, 22: 353-357.
[15] Hao X J, Liu S B, Zhao L, et al. Nucl Sci Tech, 2011, 22: 178-184.
[16] Virtex-5 FPGA Data Sheet: DC and switching characteristics, DS202 (V5.3), May, 2010.