2.1 Inspiration from neurobiology

The artificial retina working principle for high energy physics was first proposed in 2000 [4]. It is inspired by the vision mechanism in mammals. The first step of the human visual system is to project a given stimulus on the retina via the eye’s optics, which creates chemical and electrical signals that carry the visual information to the visual cortex where it is processed by the brain. Each neuron in the visual cortex is tuned to recognize a specific shape (characteristics such as orientations and edges) on a specific region of retina, which is termed a receptive field [6]. The neuron response intensity is proportional to the degree of similarity between the shape of the specific object and the shape the neuron is tuned to [6]. In this way different neurons react to the same stimulus with different intensities. The brain can extract precise information and reconstruct an image by interpolating and weighing neuron responses within limited latency [4]. Similarly, when applying this working principle to detectors, parameter space can be divided into a pre-calculated set of stored-patterns and compared with incoming hits in real time for good matching. This process can be targeted to high parallelization of information distribution and pattern-recognition systems for fast tracking in a HEP experiment.

2.2 Application in 3D space without magnetic field

To apply the retina algorithm to real-time track finding, referring to the LHCb upgrade VELO detector [9], we first set up a simple ideal model of a 100% efficient position-sensitive detector made of 8 parallel planes in the three-dimension space without a magnetic field (Fig. 1). Each plane is a 7.424× 7.424 cm square with a typical pixel size of 15×15 μm. The 8 layers are centred on the beam line and are equally spaced along the line (the z axis) with a spacing of 2.5 cm. The z-position of the layers range from z₁ = 5.7 cm to z₈ = 23.2 cm. We assume that the geometric acceptance is defined such that a particle starting from initial point (0, 0, 0) crosses each layer along a straight track with a maximum opening angle of 160 mrad in each of the xz and yz planes. The half size of the 8^th layer along the x and y axes is equal to the product of z₈ and the (θ_k,x,y). A particle passing through this detector will produce a measured hit with coordinates P (xk, yk, zk) on each layer k (k=1,2 8).

Fig. 1.Full-screen View

A cellular unit in the (u, v) parameters space (right) identifies a specific physical track that is a set of hit coordinates P (xk, yk, zk) in the detector (left).

Suppose that every trajectory of a charged particle is a straight line starting from the point (0, 0, 0) and can be described by two parameters (u, v). A two-dimensional parameter space (u, v) is made that coincides with the detector layer 8^th that is positioned at z = 23.2 cm. It is noted that (u, v) correspond to trajectory patterns in this parameter space plane rather than hits (x, y) of charged particle trajectories in this detector layer plane. In what follows, we discretize the parameter space (u, v) into a number of cells (treated as patterns) and label each cell with (ui,vj). The granularity or the binning depends on the resolution we want to achieve on the track parameters. The centre of each unit (ui, vj) identifies a track through 8 planes with an array of intersections ($x_k^{ij}$, $y_k^{ij}$, zk). This is why we create a track mapping between hit coordinates P (xk, yk, zk) and the (u, v) parameter space as shown in Fig. 1. In the current simulation, no experimental effects such as detector noise, detector efficiency or multiple scattering are added.

For each incoming r^th hit on layer k, the distance ${(s_{ij\mathrm{,}k}^r)}^2$ = ${(x_k^r-x_k^{ij})}^2$ + ${(y_k^r-y_k^{ij})}^2$between the measured hit P ($x_k^r$, $y_k^r$, zk) and the intercept ($x_k^{ij}$, $y_k^{ij}$, zk) corresponding to the cell (ui,vj) should be calculated. A weight function (response) is given by Eq. (1).

where σ is a parameter of the algorithm which can be adjusted to optimize the sharpness of the responses of the cells. Finally, the (ui, vj) cell response R_i,j equals the sum of the weights over all hits present in all the detector layers.

The overall response of the retina algorithm are obtained by calculating Rij for all cells in the (u, v) parameter space. Therefore for each incoming hit in an event, the algorithm computes the weighted distance of that hit corresponding to each intersection. The weighted distances are accumulated over all event hits. In general this procedure can be processed for all the cells on all detector layers in a full-parallel way. Fig. 2 shows a simulation with MATLAB of just one straight track reconstruction using the retina algorithm, as applied on an 8-layer-detector toy model. The parameter space is divided into an array of 212 × 212 with a grid of 350 μm in the (u, v) plane. The map below represents the intensity of the responses of all the cells, with a maximum set to 8.0. The generated track with (u,v) parameter of (2.3365, 3.0126) cm is identified by the local maximum, which in the present example is approximately (2.3288, 3.0291) cm. Note that a better precision of the extracted track parameters can typically be obtained by computing the central cell of the response cluster and interpolating cells surrounding the local maximum [7]. From this perspective, the precision of the extracted track parameters can be improved.

Fig. 2.Full-screen View

Subcell excitation levels of retina to one track in the (u,v) parameter space.

The usual steps of the artificial retina algorithm include the following:

1) Define the detector geometry, trajectory model of a charged particle, distance measurement and investigate the possible size of the parameter space and granularity;

2) Following the retina algorithm description, use weight distances to compute the response for each cell and find the best cell candidates in the parameter space.

4.1 Performance verification

This R&D work focuses on the study of the retina processor prototype. We choose the KC705 board as the hardware platform and validate two implementations of the retina algorithm: a mixed Floating-Point and Fixed-Point & LUT design. Every block of the retina processor developed in the VIVADO Design Suite is programmed using the Verilog language. We monitored the FPGA resource usage and latency associated with both designs and performed verification using ILA and VIO tools. Both implementations run at a clock frequency of 100 MHz with the possibility of running at a higher frequency (200 MHz tested).

We measure the latency of the Fixed-Point & LUT retina processor with an oscilloscope running at 10 Gbps. The histogram result in Fig. 5 shows the time difference between the data loading by the retina processor and the asserting of the maximum cell from the comparator module. The result in Fig. 5 shows that the latency mean value equals 679.5 ns with a standard deviation of 36 ps. Because the standard deviation is so small compared to the system clock frequency (100 MHz), we can assume that our Fixed-Point & LUT implementation has a fixed latency. In addition, it meets the typical trigger latency requirement that is to be less than a few microseconds.

Fig. 5.Full-screen View

Latency histogram result.

4.2 Simulation results

To quantify the retina algorithm track reconstruction performance, we compare both implementation results with software simulation results. In general, the spatial resolution of the retina algorithm is mainly driven by the total number of cells in the parameter space (u, v). In the current simulation, we generate random tracks crossing our 8-layer-detector made of pixels with a size of 15×15 μm. No detector spatial resolution or efficiency effects are added to the simulation. The centre position of the hit pixel is used as the hit position in the layer. With that detector geometry, different numbers of cells in the (u, v) parameter space have been studied. We investigated the impact of the parameter cell number on the RMS of the difference between the generated and reconstructed parameter positions in the 8^th layer. Taking into account the hardware resource usage with the growth of cell number and the degradation of RMS when lowering the number of cells, we have finally chosen to divide the (u, v) parameter space into 44944 cells with a granularity of 350 μm. The results are shown in Fig. 6 and Fig. 7, in which we histogram the differences between the generated and the computed track parameters. Figure 6 shows, respectively, the difference histograms between the generated and reconstructed parameters positions along the u coordinate (left) and v coordinate (right) for the software simulation (top) and Fixed-Point & LUT implementation in the retina processor (bottom). Figure 7 shows the same histograms between the mixed Floating-Point implementation (bottom) and software simulation (top) results. In Table 3, the Q12 RMS column lists the spatial resolutions (cm) in the (u,v) plane for both implementations against the software simulation. The simulation result shows that the retina algorithm has a good performance because it can always identify the best parameter location with our ideal detector. Under this condition, the uniform distribution of the differences between the generated and reconstructed track parameters shown in Fig. 6 and Fig. 7 follow the distribution of the track parameters that we generated, which is a uniform distribution. In addition, our retina processor is capable of providing a track resolution of 99 μm in both implementations and their performance are close to the level of the software results. Considering the FPGA resource usage and latency we investigated in Sect. 3, the Fixed-Point & LUT design offers a better choice for retina algorithm implementation. Note that, both implementations use a 12-bit Fixed-Point for the fraction, and the Floating-Point processing block uses 8 bits for exponent and 23 bits for fraction.

Fig. 6.Full-screen View

Comparison of the spatial resolution (cm) in the (u,v) plane for the Fixed-Point & LUT implementation against the software simulation (sw).

Fig. 7.Full-screen View

Comparison of the spatial resolution (cm) in the (u,v) plane for the mixed Floating-Point implementation against the software simulation (sw).

In the Fixed-Point & LUT design, we also investigate the fixed-point spatial resolution for 12 bits and 10 bits for the fraction. The performance comparisons between Fixed-Point & LUT implementation against the software simulation are summarized in Table 3. It is indicated that when we change the number of fixed-point fractional bits from 12 bits (Q12) to 10 bits (Q10), the spatial resolution (cm) in the (u,v) plane of our retina processor degrades by 25% but remains much better than the granularity of the (u,v) parameter space.

4.3 Hardware limitation

Because the Fixed-Point & LUT design provides high potential for the growth of parameter space cells that can be processed at one time, our goal is speed, and we want to find the limitation on the KC705 hardware platform.

The plane size of the detector model is only a few square centimetres, and a 32-bit fixed-point coordination representation is somewhat of an overkill; therefore we choose to use 20-bit fixed-point with 12 bits in the fraction part in the following Fixed-Point & LUT design. In addition, BRAMs are mainly used for eight 32 × 32 bits Look-Up Tables per cell. To save memory resources, we use distributed ram to replace BRAM, which is sufficient for our design requirement. These optimizations further economically improve the Fixed-Point & LUT design performance. We then expand the system size from 6 cells to 25 cells. As shown in table 4, the main logic resource costs (LUT, FF, and DSP) of the FPGA almost linearly increase (Fig. 8), and the limitation will mainly depend on the DSP. Therefore, we try to use all the DSP and manage to implement 49 cells, with the comparison as below.

Fig. 8.Full-screen View

FPGA resource usage for different numbers of cells.

We observe that the resource usage is not very balanced, and the DSPs are mainly used for the 16 multiplication operations inside each cell; therefore, we can continue to increase the number of cells by using LUT and FF to implement the multiplication operation. Finally, we fit 61 cells with 49 DSP based and 12 LUT and FF based multiplications into one KC705.