Tuning control system of a third harmonic superconducting cavity in the Shanghai Synchrotron Radiation Facility

SYNCHROTRON RADIATION TECHNOLOGY AND APPLICATIONS

Tuning control system of a third harmonic superconducting cavity in the Shanghai Synchrotron Radiation Facility

Peng-Peng Gong，

Yu-Bin Zhao，

Hong-Tao Hou，

Zhi-Gang Zhang，

Xiang Zheng，

Xiao-Yun Pu，

Kai Xu，

Qiang Chang，

Jian-Fei Liu

Nuclear Science and Techniques

Vol.30, No.10

Article number 157

Published in print 01 Oct 2019

Available online 01 Oct 2019

DOI：10.1007/s41365-019-0669-0

37601

Beam lifetime is dominated by Touschek scattering at the Shanghai Synchrotron Radiation Facility (SSRF). Touschek loss rate is affected by probability for scattering beyond the RF acceptance and the volume charge density of the bench. In the phase II upgrade of the SSRF, a third harmonic superconducting cavity will be used to enhance the Touschek lifetime by lengthening the bunches. The Touschek lifetime improvement factor is affected by the voltage of a harmonic cavity. To stabilize the cavity voltage, a tuning control system was designed to control it. The design of the tuning control system was based on the SSRF third generation low-level RF control system. Some hardware and specialized algorithms were redesigned to fit the harmonic cavity control. The design of the tuning control system is complete, and the control system has been tested. The test result shows that the fluctuation of amplitude is < ±0.34% within 1.5 h, which satisfies the stability requirement.

Passive harmonic cavityLow level radio frequencyShanghai Synchrotron Radiation FacilityTouschek lifetime

1 Introduction

In the Shanghai Synchrotron Radiation Facility (SSRF), the main factor that affects lifetime is Touschek scattering [1-3]. This is because of the low emittance (about 3.9 nm∙rad) and short bunch length (about 14 ps) of the SSRF [2, 4]. To increase the beam lifetime and suppress instability [3, 5-8], a third harmonic cavity is planned for use in the SSRF [9, 10]. This cavity is a superconducting cavity and its voltage, which can modify the longitudinal distribution, is induced by the beam itself. There is no need for an external power source because the harmonic cavity works in passive mode [7, 10]. For a passive harmonic superconducting cavity, the absolute value of the detuning angle between the beam and harmonic voltage is almost 90 degrees [11, 12].

Currently, only two facilities in the world: ELETTRA (Italy) and SLS (Switzerland) have been successful using superconducting harmonic cavities in storage rings [13, 14]. To extend the lifetime of the motors, an active feedback loop is not used in the SLS [15]. The design of the tuning control system at the SSRF draws on harmonic cavity (normal cavity) control systems of the HLS (China) and ALS (USA) [16, 17]. In the SSRF, the lifetime improvement mainly depends on the voltage of the harmonic superconducting cavity for an ultra-high quality factor [10-12]. The purpose of the tuning control system is to make the voltage fluctuation < ±1%. The tuning control system was developed from the SSRF third generation low level radio frequency (LLRF) control system.

2 Third harmonic superconducting cavity

The voltage of a third harmonic superconducting cavity can be given by [2, 11]

V_{b} \approx - I_{dc} \frac{R_{s}}{Q} \frac{f_{hrf}}{Δ f} cos (n ω_{rf} τ - ψ_{h}),

(1)

where $I_{dc}$ is the beam current, $R_{s}$ is the harmonic cavity shunt impedance, $Q$ is the quality factor of harmonic cavity, $f_{hrf}$ is the resonant frequency of harmonic cavity, $f_{rf} = ω_{rf} / 2π$ is the main RF frequency, $ψ_{h}$ is the detuning angle of the harmonic cavity, n is the harmonic number of harmonic cavity, $Δ f = f_{hrf} - n f_{rf}$ is the detuning frequency of the harmonic cavity. The relationship between the detuning angle and detuning frequency can be given by [2, 11]

\tan ψ_{h} = 2 Q \frac{Δ f}{f_{hrf}} .

(2)

The design parameters for the harmonic cavity are given in Table 1. According to equation (1), the detuning frequency ( $Δ f$ ) was calculated to be 22 kHz. From equation (2), if the detuning frequency is greater than 5 Hz, the detuning angle is greater than 89 degrees and less than 90 degrees. As a consequence, the detuning angle is almost unchanged during operation of the harmonic cavity. The purpose of the tuning control system is to control the harmonic voltage ( $V_{c} = I_{dc} \frac{R_{s}}{Q} \frac{f_{hrf}}{| Δ f |}$ ).

Parameters of SSRF harmonic cavity.

Parameters	Value
Beam current (mA)	300
Harmonic number	720
Main RF voltage (MV)	5.4
RF frequency (MHz)	500
Revolution frequency (kHz)	~694.4
Main RF cavity R/Q (Ω)	44.5
Harmonic RF voltage (MV)	1.8
Harmonic cavity R/Q (Ω)	88
Harmonic cavity operating Temperature (K)	2
Quality factor	~1 × 10¹⁰

According to Eq. (1), harmonic voltage only depends on the beam current and detuning frequency. Thus, the harmonic voltage can be controlled by fine tuning the resonant frequency of the harmonic cavity.

In simulation, the frequency sensitivity of the harmonic cavity is about 1.4 kHz/μm. To improve tuning accuracy, a fast tuner (piezo) is applied in the tuning system of the harmonic cavity.

The tuning control system consists of a front-end down-converted module, a digital processing module, and a tuner control module. First, RF signals from the harmonic cavity, beam position monitor, or master oscillator (as phase reference) are processed by the front-end down-converted module to obtain intermediate frequency (IF) signals. Then, the IF signals are sent to a digital processing module. There, the IF signals are sampled to get the state parameter of the harmonic cavity; then, tuning amounts are calculated and sent to the tuner control module. Finally, the tuner control module causes the tuner to actually tune the harmonic cavity. A simplified schematic of the tuning control system is shown in Fig.1.

Fig.1.

Brief schematic of the harmonic RF control system.

3 Tuning control system

3.1 Front-end down-converted module

The front-end down-converted module converts RF field signals to intermediate frequency signals before being sampled by an analog-to-digital converter (ADC). The front-end down-converted module consists of a LO signal board and a down-converted board. In order to be compatible with the SSRF LLRF control system, the frequency of the IF signal is set to 31.25 MHz, and the ADC sample rate is set to 25 Msps [18, 19].

In the tuning control system, there are two kinds of RF signals. The frequency of the RF signals from a beam position monitor (BPM) and master oscillator is about 500 MHz. The frequency of the pickup signal from the harmonic cavity is about 1.5 GHz.

The local oscillator of 500 MHz RF signals (LO_2 in Fig.1), of which the frequency is about 468.75 MHz, is obtained by mixing a reference signal with the 31.25 MHz signal obtained by dividing the reference signal frequency by 16.

For 1.5 GHz RF signals, the frequency of the RF signal is three times that of the reference signal, and it is not easy to get a suitable local oscillator signal directly. Considering the linear dynamic range and phase noise of the local oscillator, a scheme based on a frequency multiplier is used to generate a local oscillator of which the frequency is 1468.75 MHz [20]. The reference signal is input to the frequency multiplier to get a 1000 MHz signal; then is mixed with the 468.75 MHz local oscillator (LO_2 in Fig.1) to get the 1468.75 MHz local oscillator (LO_1 in Fig.1).

The LO signal board, of which the size is 6U as defined by the CompactPCI specification, is designed to implement the local oscillator generation function. A simplified schematic of the LO signal board is shown in Fig.2.

Fig.2.

Brief schematic of the LO signal board.

Through the down-converted board, four RF signals are down-converted to 31.25 MHz IF signals. Two channels are designed for processing 500 MH RF signals, and two channels are designed for processing 1.5 GHz RF signals in the down-converted board. The size of the down-converted board is 6U as defined by the CompactPCI specification. A simplified schematic of the down-converted board is shown in Fig.3.

Fig.3.

Brief schematic of the down-converted board.

3.2 Digital processing module

The digital processing module consists of an SSRF third generation LLRF DSP board and a CompactPCI CPU board. This LLRF DSP board supports six-channel ADC for IF signal input, a two-channel digital-to-analog converter (DAC) for RF signal output, and a high-performance clock generator for clock configuration. Algorithms can be flexibly implemented by a large-capacity field programmable gate array (FPGA) on the LLRF DSP board. The CompactPCI CPU board is used for communicating with the upper monitor and for configuring loop parameters. The status of the harmonic cavity can easily be obtained using the experimental physics and industrial control system (EPICS) that is installed on the CompactPCI CPU board.

All the control logic is realized on the LLRF DSP board, and the algorithm used for IF signal processing is the same. First, IF signals with frequency of 31.25 MHz are sampled by the ADC, with a sample rate of 25 Msps. The ratio of the IF signal frequency to the sample clock frequency (5:4) satisfies the necessary relationship for in-phase and quadrature (IQ) sampling. The serial sampling sequences are I/Q/-I/-Q. Secondly, the sampling sequences are rotated by the rotation algorithm module and calculated by a coordinate rotation digital computer (CORDIC) algorithm module. After this the phase and amplitude of all IF signals can be gotten. Finally, the amplitude and phase are filtered using a cascade integrator comb (CIC) algorithm module. A brief schematic of the control logic is shown in Fig.4.

Fig. 4.

Brief schematic of the control logic.

After IF signal processing, the harmonic voltage (V_c) and the phase (Δθ) of the pickup signal relative to the reference signal can be obtained. According to Eq. (2), the detuning angle is extremely sensitive at the detuning frequency near 0 Hz. It can be judged by Δθ that the detuning frequency is greater than or less than 0 Hz to avoid the harmonic cavity working in the wrong status ( $Δ f$ < 0 Hz). If the harmonic cavity works in the wrong status, the harmonic voltage is kept below 0.1 MV. The beam current ( $I_{dc}$ ) can be calculated from the amplitude of the BPM signal and beam current correction factor (k_Q(x, y), where x and y are the beam position offset of the BPM chamber center) [21]. Under the condition that the beam position offset is small (x < 6 mm, y < 6 mm), the change of the position correction factor is < ±7% (0.916 < k_Q(x, y) < 1.05) for the BPM chamber in the SSRF [21]. In this control system, the beam current is a trigger signal for a control switch. A quantization error of ±7% of the beam current due to the position correction factor is acceptable.

The functions of the control switch module, as shown in Fig.4, are tuner control and interlock protection. The control switch module controls tuner switches by controlling the variables that are input to the proportional integral (PI) module. The slow tuner (motor) and fast tuner (piezo) do not work at the same time; they work alternately to make control simple and reliable. According to different situations, there are three conditions of the beam current, and the control status is switched for different beam current conditions. When the beam current is less than 30 mA, the harmonic voltage is maintained below 0.1 MV by the slow tuner for the purpose of protecting the harmonic cavity. When the beam current is > 30 mA and < 280 mA, the set point of the harmonic voltage (Vset) is adjusted according to the beam current to keep the detuning frequency near 22 kHz. Under this condition, Vset can be given by

V_{set} = I_{dc} \frac{R_{s}}{Q} \frac{f_{hrf}}{Δ f}, (Δ f = 22 kHz) .

(3)

When the beam current is larger than 280 mA, the set point of the harmonic cavity is 1.8 MV. Under this condition, the tuning work is mainly done by the fast tuner. The tuning range of the fast tuner, which works at room temperature, is about 20 kHz. Therefore, the fast tuner can meet a tuning requirement that is about ±5 kHz. The slow tuner does not work until the range of the fast tuner has been exceeded. The tuner status and control parameters are shown in Fig.5.

Fig. 5.

Tuner status and control parameters under different beam current conditions.

3.3 Tuner control module

The tuner control module provides interfaces for the interlocking system, motor driver, and piezo driver. All functionality of the tuner control module is integrated on the tuner control board, which is a 6U rear panel I/O board, as defined by the CompactPCI specification. On the tuner control board, all the digital signals related to the tuner or interlocking system are input or output through the optical coupler. For high tuning accuracy, an AD5763, which is a dual, 16-bit, bipolar voltage output DAC, is used for piezo control.

4 Test for control system

4.1 Front-end down-converted module test

The noise of the local oscillator can be mixed into the IF signal. Therefore, the phase noise of the local oscillator is important for a down conversion. The LO signal board is tested by analyzing the phase noise of the 1468.75 MHz local oscillator (LO_1). The phase noise of the LO signal depends on the design of the LO signal board and the phase noise of the reference signal. In the test, an E8663B analog signal generator provides a 500 MHz RF signal as the reference signal, and a 1468.75 MHz LO is input to the E5052B signal source analyzer to analyze the phase noise. The test result is shown in Fig.6, and the root mean square (RMS) of the jitter is about 61.79 fs.

Fig.6.

LO_1 (1468.75 MHz) phase noise measurement over the bandwidth (10 Hz to 10 MHz).

To detect weak signals, the linear dynamic range of the front-end down-converted module should be greater than 30 dB. The setup for linearity measurement is shown in Fig.7. In the test, two analog signal generators (E8663B and E4438C) are used, and the 10 MHz signal from the E8663B is input to the E4438C to lock the phase of the RF signal. The E8663B analog signal generator outputs a 500 MHz RF signal as a reference signal, of which the power output is fixed to 3 dBm. The reference signal is input to each part of the tuning control system after being divided by the power splitters. The RF signal, of which the frequency is 500 MHz or 1.5 GHz, is output by the E4438C analog signal generator, and is then input to a different channel of the down-converted board. The IF signal output is input to the E4445A spectrum analyzer for linear analysis. As is shown in Fig.8, the linear dynamic range of the down-converted board is greater than 60 dB.

Fig.7.

Setup for linearity measurement.

Fig.8.

Linear test for down-converted board: channel 1 and channel 2 are designed for 1.5 GHz down conversion; channel 3 and channel 4 are designed for 500 MHz down conversion.

The frequency of all channel output signals is 31.25 MHz, and cross-talk among channels directly affects the detection accuracy of the tuning control system. The isolation measurement of the down-converted board is tested with the same setup used for the linearity measurement (in Fig.7). In Table 2, the isolation of the down-converted board is better than 81 dB.

Cross-talk between IF ports (dB).

	Channel 1	Channel 2	Channel 3	Channel 4
Channel 1	X	-81.2	-101.7	-103.1
Channel 2	-81.9	X	-96.3	-99.6
Channel 3	-93.8	-92.2	X	-90.2
Channel 4	-86.9	-88.9	-97.4	X

4.2 Simulation of the algorithm for IF signal processing

During harmonic cavity operation, the detuning frequency of the harmonic cavity is about 22 kHz. The pickup signal is affected by the bunch trains filling pattern of the SSRF [3, 22]; thus, the frequency components that offset the integer multiple of the revolution frequency (about 694.4 kHz) can be found in the pickup signal. The interference of these parts of the frequency components is difficult to filter out by a filter on the down-converted board. For this reason, the CIC algorithm module was designed to reduce this interference and other high frequency noise. The algorithm for IF signal processing was simulated using EDA software. The results of the gate level simulation are shown in Fig.9. The IF signal data mixed with the 694.4 kHz frequency component is input to the digital processing module. The amplitude and phase can be demodulated by the CORDIC module within 1 μs, and the phase and amplitude of the CORDIC module output can be used as an interlocking system. The CIC algorithm can be completed in approximately 6 μs. The algorithm of IF signal processing can satisfy the need for fast and high-precision processing of the signal, and it can also significantly reduce the effects of high frequency noise and improve system reliability.

Fig.9.

Gate level simulation of the algorithm of IF signal processing. a) IF data mixed with 694.4 kHz frequency component input, b) CORDIC algorithm module amplitude output, c) CORDIC algorithm module phase output, d) Amplitude output through CIC algorithm module, e) Phase output through the CIC algorithm module.

4.3 Closed loop test for the tuning control system

The tuning control system realizes fine tuning control of the superconducting cavity. It is difficult to test the accuracy of the control system using a normal conducting cavity because of its low Q value. In the test, the calculation model of the harmonic cavity was designed by computer. The setup for the closed loop test is shown in Fig.10.

Fig.10.

Setup for the closed loop test.

First, the piezo displacement is detected by a displacement sensor in the piezo driver, and then the displacement data are input to the computer. The function of the piezo driver is to amplify the voltage of the DAC output. Second, the harmonic voltage is calculated from the piezo displacement and the beam current set by the computer. Third, the RF output power of the analog signal generator of which the RF output is used as the pickup signal is set by the computer. Finally, the tuning control system adjusts the piezo control voltage according to the demodulated IF information.

The piezo voltage data input to the DAC of the tuner control board and the amplitude of the pickup signal are recorded by EPICS. The closed loop test data are shown in Fig.11.

Fig.11.

Closed loop test data within 1.5 hours. a) Piezo voltage data for DAC; b) Amplitude of the pickup signal (V_set = 9000).

Test results show that the tuning control system can adjust the piezo displacement according to the amplitude of the pickup signal, and the fluctuation of the amplitude was less than ±0.34% within 1.5 hours. The tuning control system can realize high precision amplitude control of the harmonic voltage. The hardware of the tuning control system is shown in Fig.12.

Fig.12.

All modules of the tuning control system are integrated in a CPCI chassis.

5 Summary

In this paper, the design and construction of a tuning control system for a third harmonic cavity are described. The control system adjusts the harmonic voltage by tuning the resonant frequency of the harmonic cavity. The tuning control system has been completed. The hardware and software for each module has been tested. All parameters meet the control requirements. In addition, the function and accuracy of the control system were initially verified in a closed loop test. The amplitude can be controlled within ±0.34%.

References

B.C. Jiang, Z.T. Zhao, G.M. Liu,

Study of Touschek lifetime in SSRF storage ring

. High Energy Phys. Nucl. Phys. 30:693-698(2006).