2.1 Devices under test (DUT) details

The 1-T anti-fuse PROM has a fast read speed and high storage density (8 Mbits and 16 Mbits). Its memory unit is shown in Fig. 1. A non-volatility memory cell is achieved with the thick and thin oxide anti-fuse technique. The cell was fabricated as a single transistor with a thin/thick oxide gate [10]. The thin oxide region (4.5 nm) is penetrated under the action of high voltage, leading to a conductive channel, while the thick part (7.5 nm) can withstand high voltage with its high resistance. The breakdown position is fixed on the edge of the thick and thin oxide film, which is called the Program Area. The DUTs were decapped before exposure in order to make swift heavy ions reach the sensitive regions.

Fig. 1Full-screen View

(Color online) Diagram of thin/thick gate oxide anti-fuse memory unit

Each DUT adopted a 130-nm silicon epitaxial process with 16 layers including passivation and metal on top of the die. Compared with 8-Mbit PROMs, the storage of a single bit in a 16-Mbit PROM is achieved by two anti-fuse memory units in order to enhance its programming reliability. A guard ring structure can provide spatial and electrical isolation in CMOS circuits in order to prevent a Single Event Latch-Up (SEL). We fabricated p+ guard rings connected to the ground and enclosed the n+ sources in order to reduce the minority carriers in an NMOS. In a PMOS, n+ guard rings connected to high voltage were used to prevent the influence of minority carriers in the transistor. An EDAC verification code generated by a Hamming code and TMR in an internal latch employed a triple modular voter circuit. EDAC and TMR are two main SEU-hardened methods that will be further analyzed in Sect. 3.

The DUTs were utilized in dynamic mode at room temperature, and the frequency was controlled at 20 MHz (cycle time: 50 ns) with a 1-A current limitation. The cycle time can affect the number of captured errors created by particle-induced transient pulses in peripheral CMOS circuits, and then can influence the effect of our error-correction methods (EDAC and redundancy). The DUT was employed using a serial addressing mode to read statistics, and its memories were continuously scanned by an FPGA-based tester. In the test process, the internal data in the DUT were a 00-FF circular sequence code. Once an error was detected, the error information including its address was recorded. Any error data and abnormal currents were investigated and presented on the screen.

2.2 Heavy-ion facility and parameters

Heavy-ion testing was carried out at the Heavy Ion Research Facility in Lanzhou (HIRFL) at the Institute of Modern Physics, Chinese Academy of Sciences, and at the HI-13 Tandem Accelerator at the China Institute of Atomic Energy. The flux of incident ions can be controlled at 10⁴ ions·cm^-2·s^-1. Most irradiation tests were performed in air with heavy ions passing through a vacuum/air transition foil. Both Al foils and air were used as energy degraders to adjust the beam energy. The swift heavy-ion parameters in the experiments are listed in Table 1 [9, 11–13]. Five kinds of heavy ions were used for DUT irradiation. Both the LETs and range values were calculated by using SRIM 2013 (in Table 1). Although the HI-13 beams had inferior energy, the thicknesses of all upstream multilayers could still be penetrated.

2.3 Pulsed-laser testing system

A picosecond pulsed laser was employed to irradiate the DUT and gather the SEU signals in a timely manner. The test system (Fig. 2) was composed of an optical module, a high-energy pulse laser (with 1064-nm center wavelength and 25-ps pulse width), optical polarization, and an attenuation module. Laser pulse polarization and attenuation were achieved by combining filters that attenuated the beam to fixed amounts with polarizer/half-waveplate continuous variation. An energy monitoring and controlling system with operating software was used to control the energy changes from 1 nJ to 30 nJ. A camera was needed to image the surface of the DUT and focused laser spot, making it possible to identify which sensitive node was being tested by the pulsed laser [14]. Additionally, a three-dimensional mobile platform provided the DUT positional parameters directly in order to retain the accuracy and stability during the experiment.

Fig. 2Full-screen View

SEE laser testing system

In the test, a topside irradiation mode with a 5-µm spot size was selected. Owing to the large feature size and low metal coverage rate in the DUT, incident photons from the top side easily reached the SEE sensitive nodes unhindered by metal interconnects or packaging [14]. Given the very small sizes of the sensitive nodes in the DUT, a stage with a step size of <1 µm should be used. The pulsed-laser parameters illustrated above can effectively characterize the SEE both spatially and temporally.

3.1 Heavy-ion SEU test

DUTs with 8-Mbit and 16-Mbit configurations were irradiated by five swift heavy ions, and the SEU data were collected. SEUs in the DUTs mainly contained dynamic bit errors and address errors, as shown in Table 2. For the advanced thin/thick gate oxide anti-fuse process in the DUT memory block, each unit exhibited a high anti-irradiation performance. However, a few dynamic bit errors in the readout during irradiation were observed. This may have resulted from dynamic upsets in the output buffer, thus making a single bit error appear. The internal address counter in the DUT stores the information of the current address and any increments or resets. If a counter is upset, a subsequent reading will proceed from the new (upset) address [2]. The address encoded in the DUT identifies the current location. Apparently, most upsets in the counter may be owing to a single bit, but long-lasting multiple-bit upsets were also seen.

Based on the recorded upset data, a Weibull function (as given below) was used to fit the heavy-ion-induced SEU data.

where σ (cm²·bit^-1) is the SEU cross section in terms, σ_sat (cm²·bit^-1) is the saturation upset cross section, LET_th is the minimum LET to observe an error in the stored data, s is a dimensionless exponent, and w is a width parameter. The total gathered errors are shown in Fig. 3.

Fig. 3Full-screen View

SEU cross section of total errors in 8-Mbit and 16-Mbit PROMs vs. LET

For 8-Mbit PROMs, the LET threshold of the SEU is about 9.2 MeV·cm²·mg^-1, with the saturation cross section at 1.0 × 10^-5 cm²·device^-1. The 16-Mbit PROM has a similar LET threshold (9.6 MeV·cm²·mg^-1) but a higher-saturation cross section at 2.7 × 10^-5 cm²·device^-1. The thresholds of two DUTs are almost identical, while the 16-Mbit PROM has a larger interaction area for charge deposition and collection, causing the probability for the interactions between heavy ions and the sensitive volumes in 16-Mbit PROM improved. This leads to a negligible increase in the SEU saturation cross section of the 16-Mbit PROM. However, when the saturated cross section values are normalized per bit, the two DUTs are roughly the same: 1.3 × 10⁻¹² cm²·bit^-1 (8 Mbit) and 1.7 × 10⁻¹² cm²·bit^-1 (16 Mbit).

Upsets in address counters and I/O pairs result from a single bit, although a few multiple-bit upsets were observed. All of the address errors were measured and fitted by a Weibull function, as shown in Fig. 4. In the figure, the LET thresholds of the 8- and 16-Mbit PROMs are approximately 21.1 MeV·cm²·mg^-1 and 18.1 MeV·cm²·mg^-1, respectively, with a saturation cross section at 9.7 × 10⁻⁶ cm²·device^-1 (1.2 × 10⁻¹² cm²·bit^-1) and 1.3 × 10⁻⁵ cm²·device^-1 (8.1 × 10⁻¹³ cm²·bit^-1), respectively.

Fig. 4Full-screen View

SEU cross section of 8-Mbit and 16-Mbit PROM address errors vs. LET

The LET thresholds of the address data are higher than those of the stored data, but they play a primary role in the SEU rates with LET values between 22.4 and 37.6 MeV·cm²·mg^-1. For several LET values, the rates of the address data can exceed 90%. A superior threshold may be derived from high reinforcement in the I/O ports and the TMR structure of the address counters. Above all, large I/O ports need to deposit more charge to trigger an upset, and a large critical charge is difficult to create in low-LET-irradiation conditions. On the other hand, all of the address counters with basic CMOS structures have TMR consolidation. An error signal pulse introduced by the external test environment must be loaded to significant parts such as the reset sites, and it eventually passes through the voter. These restrictive conditions increase the upset threshold.

PROMs with 8-Mbit and 16-Mbit configurations adopt the same radiation hardening structure and obtain similar irradiation testing results. This shows that the sensitive circuits of these two devices are the same, and their anti-irradiation performance is mainly determined by reinforcement in the sensitive circuits. Thus, their overall anti-irradiation ability is better than that of several foreign products investigated in [1, 2]. Here, EDAC and TMR, as two main reinforcement methods, decreased the saturation cross section of the error data in the 8-Mbit PROM and 16-Mbit PROM by approximately 10^-12 cm²·bit^-1, indicating a good capacity to resist SEU.

The EDAC verification code adopted by the DUTs is generated by a Hamming code with 32 plus 8 structures. In irradiation experiments, the EDAC function was used continuously. According to the data stored in the memory cells and the examined algorithms designed as EDAC codes, the testing system can determine whether errors appeared, and make corrections immediately. The TMR mode in the internal latch (Fig. 5) employs three logic cells to store the same data and select the correct output by a triple modular voter circuit.

Fig. 5Full-screen View

TMR structure in latch circuit

Error signals caused by heavy ions and captured by a latch or register need to satisfy three basic conditions: existence paths from the struck node to a latch or register, a proper arriving time, and a necessary profile at the latch input. Under TMR reinforcement in the latch circuits, even if an error signal is captured by the latches, there is still no guarantee that it will be transmitted to the output and pass the TMR voter.

Compared to the statistics in the heavy-ion test in Ref. [2], the TMR structure in the latch circuit can reduce the upset rates to a great extent. However, the hardened effects of the TMR and EDAC techniques are affected by the cycle time. With the error accumulations in one period, dynamic bit errors may not be corrected by a one-error-correction Hamming code and are distinguished by a triple redundant voter in time, thereby providing the error information as the output.

Additional large-fluence swift heavy-ion irradiation was used to check the program redundancy technique that existed in the 16-Mbit PROMs, which were created to enhance the reliability and decrease the influence of hard errors in memory cells. After high LET ²⁰⁹Bi (91.1 MeV·cm²·mg^-1) irradiation for over a decade of cycles (each cycle was tested with nearly 10⁸ ions), several hard errors appeared only in the 8-Mbit PROM (as shown in Table 3), although the probability was extremely low and the rates were lower than 10^-6. These persistent hard errors can be interpreted as irradiation damage created by swift heavy-ion irradiation in their program area, as shown in Fig. 6.

Fig. 6Full-screen View

(Color online) Generation of persistent hard error in anti-fuse structure

Because of the thin and sensitive program areas in anti-fuse transistors, a large fluence of swift heavy ions can form surface roughness, ion tracks, irreparable damage, and can cause several unprogrammed cells to eventually become programmed. The experimental results revealed that an irreparable program can be created by high-LET ²⁰⁹Bi particles, resulting in the occurrence and detection of 0-to-1 upset errors. However, taking both the space LET spectrum and the DUTs’ actual working states into consideration, this hard damage may not exist over a decade in geosynchronous orbit or medium earth orbit. This means that DUTs without programming-redundant design are still suitable for general space missions. However, for long-term space missions, this reliability-enhanced design seems to be a better choice.

3.2 Laser SEU test

Laser mapping images with sensitive areas marked by colored points are shown in Fig. 7. The scanning energy was continuously changed from 1 nJ to 30 nJ, and the experimental manipulation was repeated to radiate the DUT in the full-exposure area [15,16]. The energy values in Fig. 7(a), (b), and (c) indicate the laser thresholds of the power source, I/O pairs, and internal circuits, respectively, by comparing them with the schematic view of the DUT in Fig. 7(d). Each mapping image is repeated at least three times.

Fig. 7Full-screen View

(Color online) Mapping results by picosecond pulsed laser with energy of (a) 8.5 nJ, (b) 13 nJ, (c) 27 nJ, and (d) 30 nJ (schematic view)

The internal power source module in the upper right corner of Fig. 7(d) is the most sensitive part because the circuit around the power source is extremely difficult to reinforce. The experimental results proved the significance of this issue. In addition, the I/O pairs connected to the data output in the peripheral circuits showed errors when the laser energy was 13 nJ or higher. This corresponded to the higher threshold in the large reinforced I/O pairs of the heavy-ion test. Then, a few error data items near the center of the DUT occurred; these increased in areas and at rates where the laser energy increased.

Errors that occurred in the middle area of the DUT are reading comparison circuits. These dynamic circuits are used to store and compare the data in continuous modes. When ions or a laser strikes, the transient pulses eventually appear and propagate in the comparison circuit. When laser energy increases, the data in the latch circuits has a few errors. Nevertheless, the increased error rates and sensitive areas in the reinforcement latch circuits can be neglected.

The laser experiment verified the excellent radiation resistance of the DUT for the areas of stored data that were not very sensitive to photons, or where upsets may be detected and corrected by the EDAC code TMR voter in time. The address bits have a high SEU threshold, but when the laser energy is higher (>8.5 nJ), error data cannot be corrected by the voter and EDAC in time owing to the surging of long-lasting and successive upsets.

The power source, I/O pairs, and peripheral circuit without hardness designs are SEU-sensitive areas revealed by laser irradiation. Using only a large-size hardness technique in the I/O pairs cannot totally prevent SEUs. Nevertheless, I/O blocks in the PROM will not be operated until the FPGA demands to be configured in an actual space environment. This takes effect under the intermittent operation working condition only when the stored information required to be transmitted rather than under the continuous working mode in the entire SEE ground test, thus sharply declining the SEU risk.

In addition, without further reinforcement in the I/O pairs, the saturated cross section of this PROM was fairly small already, which revealed its excellent antiradiation performance to satisfy space requirements.

Accelerated ¹⁸¹Ta ions with an energy of 12.5 MeV·u^-1 were used to reexamine the pulsed laser testing results by adding 2-mm Al foils above the internal power source on the right part of the DUT and all I/O pairs. The calculated saturation cross section was 4.1 × 10⁻⁶ cm²·device^-1, which declined significantly when compared with its initial value (2.7 × 10⁻⁵ cm²·device^-1). This verified that in the pulsed laser test, the I/O pairs and internal power source contributed the majority of the upset rates.

4.1 RPP model extraction

Simulation tools based on the Monte Carlo method were used. The effective calculation area was divided equally per bit and can be calculated by the following formula:

where N is the total number of bits in the PROM. S_total is the actual area of the DUT, and S_bit is an equivalent single-bit area. Then, the sensitive area per bit per square centimeter (σ_bit) can be calculated based on the experimental results summarized above. For a 16-Mbit PROM, σ_bit is 1.7 × 10^-12 cm².

Experimental heavy ions were used to irradiate the model of the PROM. Beams were set at normal incidence with a zenith angle of 0º to directly radiate the DUT model built in Fig. 8. The particle fluence was controlled at 4.0 × 10¹⁰ ions·cm^-2. Based on the device parameters and Eq. (2), the depth of the sensitive volume was set at 1 μm. The relation between the energy deposition in the entire sensitive volume and the cross section in space can be calculated by using the Crème-MC simulator [17–19].

Fig. 8Full-screen View

(Color online) Extracted RPP model based on ground heavy-ion test

The collected charge (Q_c) can be determined based on the results of the RPP selection and their ascertained energy deposition. For Si devices, Q_c associated with an individual particle event can be calculated by a linear combination of the energy deposited in each volume (E_i). This can be written as [17]

The depth (H_sv) of the volume is related to the critical charge (Q_cri). Since the energy to produce an electron hole pair in silicon is a constant equivalent to 3.6 eV, Q_cri can be defined by [17]

where LET_th in Eq. (4) indicates the LET threshold values, and H_sv is in micrometers. By combining Eq. (3) and Eq. (4), E_i can be determined [17]. It is obvious that the cross section of ²⁸Si and ³⁵Cl is slightly below 10^-13 cm²·bit^-1, which is close to the LET threshold in the heavy-ion test (around 10^-13 cm²·bit^-1). In addition, the cross section obtained by the simulation of ²⁰⁹Bi is approximately 1.9 × 10^-12 cm²·bit^-1, which matches the experimental saturation cross section at 1.7 × 10^-12 cm²·bit^-1. Thus, the established RPP model for space prediction fits well with the experimental results.

4.2 Calculation of error rates

The prediction of heavy-ion SEU rates (R) in space is accomplished based on the measured cross sections in the heavy-ion test and the ion flux in a given orbit obtained by Crème-96 [20, 21]. It is calculated by

σ(LET) is the effective cross section, i.e., it can be averaged on all solid angles (as shown in Fig. 8). The sensitive volume was irradiated by heavy ions in space from 4π solid angles. Here, Φ_eff is a differential ion-flux spectrum for a given shielding thickness in geosynchronous orbit in a solar maximum condition [20].

Fig. 9 proves that with a shielding thickness over 3 mm, Al may provide promising results in reducing SEU rates. Based on the constructed RPP model in Creme-MC and the calculated Q_cri, the SEU rates caused by heavy ions in space were calculated and are shown in Fig. 10. Shielding by 10-mm Al produced a superior protection effect with a low event rate of 6.26 × 10^-13 upset·bit^-1·day^-1. The calculated event rate is matched to continuous working conditions such as a ground test. This may be a few orders larger than its actual intermittent operation mode in space.

Fig. 9Full-screen View

Heavy-ion energy after penetrating different shielding thicknesses of Al

Fig. 10Full-screen View

Event rate per bit per day in geosynchronous orbit vs. shielding thickness of Al