2.1 Experimental setup

Neutron-gamma discrimination experiments were performed using the neutron-gamma source AmBe-241 at the Institute of High Energy Physics. Figure 1 shows an overview of the experimental architecture. Plastic scintillators (EJ-299-33) were used as neutron detectors. EJ-299-33, which has been proven capable of PSD [3–7], is a relatively new scintillator used for neutron detection. It exhibits some advantages over traditional liquid organic scintillators, such as increased durability and flexibility in manufacturing detectors of various sizes and shapes. Compared with the standard plastic and liquid scintillators such as EJ-301, the EJ-299-33 scintillator exhibits a decreased light output and discrimination capability [5,6].

Fig.1.Full-screen View

Overview of the experimental architecture. A lead brick was used as the shielding.

XP2020 PMTs were coupled to EJ-299-33 scintillators to collect the output scintillation light. Pulses from the anodes of the PMTs were passed onto this module directly through coaxial lines without any signal amplification and shaping circuits. In the fast pulse sampling module, a DRS4 chip recorded the input signals continuously at 1 GSPS and 2 GSPS sampling rates in internal switched capacitor arrays (SCA). The recorded content of each sampling cell was read out and digitized with an external 14-bit resolution analog to digital converter (ADC) at a relative low frequency (33 MHz) [10,11]. The digitized waveform was then sent into the FPGA for real-time data analysis. Finally, the neutron-gamma discrimination results were transmitted to the backend PC using the UDP protocol.

2.2 Design of fast pulse sampling module

Figure 2 is the actual image of the fast sampling module. Figure 3 shows a functional block diagram of the fast sampling module. The fast pulse sampling module has four input channels on a 10 cm × 6 cm PCB. The four analog inputs are AC coupled and have an input range of 1 V peak to peak [10]. On the input side, the single end signals were converted into differential signals by TH4508 to meet the DRS4 input requirements. The differential signals were continuously sampled in DRS4. The sampling rate of the DRS4 can be programmed to 0.7–5.12 GSPS by adjusting reference clock frequencies.

Fig.2.Full-screen View

Image of DRS4 module PCB.

Fig.3.Full-screen View

Block diagram of fast sampling module.

A local trigger for each channel was generated by a fast comparator and then fed into FPGA. The local trigger threshold was adjusted by setting DAC values. The DAC also provided BIAS and ROFS DC voltage for the DRS4 chip [10]. A global trigger logic was built in the FPGA, which allowed for achieving significant background noise reduction with the smart trigger logic. The global trigger logic can be altered by reprogramming the FPGA firmware. After the global trigger was met in FPGA, the DRS4 chip stopped sampling the input signals and the contents of the frozen sampling cells were read out through the read shift registers and digitized with an external ADC (Figure 4). There is an unavoidable dead time of about 33 μs when using the full readout mode. To reduce the dead time, it is possible to read only a subset of all sampling cells by the ROI mode [10]. In real-time data analysis, only 700 out of all 1024 samples in one waveform were used for PSD. We can read out only 700 samples by the ROI mode. Therefore, the dead time can be reduced by 30 percent.

Fig.4.Full-screen View

Simplified schematics of DRS4 domino wave circuit.

2.3 Online offset calibration

The DRS4 chip contains a ring buffer with 1024 samples for each channel, as shown in Figure 4. The ring buffer is built as a chain of capacitors. The input signal is fed continuously to these capacitors. There are different offsets of 1024 sampling cells to a certain DC input owing to variations in the IC manufacturing process [13–15]. The uncalibrated data has a noise level on the order of approximately 10 mV RMS, as shown in Figure 5 (left side) [8]. A DC offset calibration is required for accurate PSD. The offset in a cell has negligible variation; therefore, it is easy to correct the offsets by using averaged values. In this work, an online DC offset calibration method using the FPGA was developed. In the offset calibration process, a high precision 0 V DC voltage generated by the on-board 16-bit DAC was connected to all DRS4 inputs and sampled [11]. The offset voltage and gain of each sampling cell were evaluated in the FPGA and then stored in random-access memory (RAM) inside the FPGA. The entire process took some milliseconds. A RAM with a 14-bit width and 1024-bit dada depth was deployed for each channel. The address of the RAM corresponded to the serial number of the sampling cell and ranged from 0 to 1023. The offset was removed while the digitized waveform streamed into the FPGA. After offset correction, as shown in Figure 6 (right side), the noise level was reduced to about 0.4 mV RMS, which, although acceptable, is slightly higher than the 0.35 mV from the DRS4 data sheet [10]. After the offset calibration, the data was sent to the integral unit and the PSD analysis unit in the FPGA. Although the total data size of one digitized pulse produced by incident neutron or gamma ray is 1792 byte, the PSD result of one incident particle event is only 8 bytes. Compared with the method that transmits the whole digitized waveform to the backend PC, under the circumstance with counting rate of 10,000 particles per second, the data rate can be reduced to only 80 KB/s when the real-time algorithm is implemented.

Fig.5.Full-screen View

Data processing flow in FPGA.

Fig.6.Full-screen View

(a) 0 V DC voltage sampled before DC offset correction; noise level is 10.5 mV RMS. (b) 0 V DC voltage sampled after DC offset correction; noise level is 0.4 mV RMS.

2.4 Energy calibration

Compton scattering dominated the interactions of gamma rays within the EJ299 plastic detector owing to the intrinsic property of the plastic scintillator and its small size (1 cm × 1 cm × 5 cm). Therefore, energy calibration was carried out by using the Compton edge energy of Cs-137 and Co-60 gamma sources in each radionuclide energy spectrum. The pulse height distributions are shown in Figure 7. The Compton edge energy of Cs-137 gamma rays is 477 keV. Energies of Compton edges for Co-60 gamma-rays are 963 keV and 1119 keV. Energy calibration was obtained by averaging the two Co-60 Compton edge values because of the small detector size (1 cm × 1 cm × 5 cm). The Compton edge energy was determined where the voltage amplitude of the Compton plateau reached 70% of its maximum intensity. The energy calibration result obtained is shown in Figure 8.

Fig.7.Full-screen View

Co-60 and Cs-137 gamma pulse amplitude distribution.

Fig.8.Full-screen View

Detector energy calibration result with Co-60 and Cs-137 gamma sources.

2.5 Real-time pulse shape discrimination

The PSD method was developed based on the difference between scintillation lights from neutron and gamma-ray interactions in the EJ299-33 scintillator. The relative ratio of the slow component to the total scintillating light depends on the type of interaction, i.e., recoiling of electrons for gamma rays and recoiling of protons for neutrons [5–7]. Neutrons were identified by a higher slow component fraction compared with that of gamma rays.

The charge comparison method is well suited for the FPGA. Accordingly, it was adopted as the method for PSD in this study [16–18]. Using this method, every signal was integrated at the same time through two separate routes in the integral unit of the FPGA. Figure 9 shows the two integral regions. The long integral region started at the peak of the pulse and extended to approximately 350 ns after the zenith of the pulse (I_long). The short integral started at the same position as the first integral and ended at approximately 20 ns after the zenith (I_short). The two regions of the integration are critical for this method, because the integration ending point can be optimized to enhance the neutron-gamma discrimination. The integration parameters can be easily modified by reprogramming the FPGA.

Fig.9.Full-screen View

Sampled signal after calibration. The plot illustrates the two integral regions for gamma- neutron discrimination.

After integration, the data was sent to the PSD analysis unit. The PSD is defined as

The ratio I_short/I_long of each channel was calculated in real time in the PSD analysis unit. The data size was reduced significantly after passing through the PSD analysis unit. Finally, the real-time PSD results were transmitted to the post-processing backend by using a gigabit ethernet link. A widely used figure of merit (FOM) method was used to characterize the discrimination capability [18]. The FOM is defined as

where $\Delta X$ represents the distance between the gamma and neutron peaks and $\delta \text{gamma}$ and ${\delta }_{\text{neutron}}$ represent the full width at half maximum of the corresponding peaks. The neutron and gamma peaks were fit with two Gaussian functions.