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Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

NUCLEAR ELECTRONICS AND INSTRUMENTATION | Updated：2022-01-14

- Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies Cover Article Enhanced Publication
- Nuclear Science and Techniques Vol.32, Issue 12, (2021)
- Affiliations：
  
  Institute of Modern Physics, Chinese Academy of Sciences,Lanzhou,China,730000;Department of Computer Science and Technology, Tsinghua University,Beijing,China,100084;School of Nuclear Science and Technology, University of Chinese Academy of Sciences,Beijing,China,100049
- Author bio：
- Funds：
- DOI：10.1007/s41365-021-00979-8 CLC：
- Published：2021-12，
  
  Published Online：13 December 2021，
  
  Received：01 July 2021，
  
  Revised：30 October 2021，
  
  Accepted：01 November 2021
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Cite this article
Ze He, Shi-Wei Zhao, Tian-Qi Liu, et al. Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies. [J]. Nuclear Science and Techniques 32(12):139(2021)
DOI：

Ze He, Shi-Wei Zhao, Tian-Qi Liu, et al. Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies. [J]. Nuclear Science and Techniques 32(12):139(2021) DOI： 10.1007/s41365-021-00979-8.

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Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies Cover Article Enhanced Publication