Magnetic flux leakage analysis and compensation of high-frequency planar insulated core transformer

Magnetic flux leakage analysis and compensation of high-frequency planar insulated core transformer 1 2 first-author 1 1 1 corresp Corresponding author, lideming@sinap.ac.cn Corresponding author, lideming@sinap.ac.cn lideming@sinap.ac.cn 1 Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Shanghai 201800, China Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Shanghai 201800, China University of Chinese Academy of Sciences, Beijing 100049, China University of Chinese Academy of Sciences, Beijing 100049, China A novel high-frequency and high power density planar insulated core transformer (PICT) applied to high voltage direct current (DC) generator is introduced. PICT’s operating principle and fundamental configuration are described, and preliminary experimental results in self-designed PICT apparatus are presented. Emphatically, magnetic leakage flux (MFL) giving rise to the output voltage drop is analyzed in detail both theoretically and by finite element method (FEM). Showing good consistency with experimental result, FEM simulation is considered to be practicable in physical design of PICT. To cancel out leakage inductance and improve the voltage uniformity, compensation capacitor is adopted and experimental verification is also presented. All shows satisfactory results. Planar insulated core transformer Load operation Magnetic flux leakage Leakage inductance Finite element analysis Flux compensation I. INTRODUCTION 1 Planar insulated core transformer (PICT) is a novel high-voltage and high power direct current (DC) generator demonstrating both properties of insulated core transformer (ICT) [ 1 1 - 3 3 1-3 ] and planar transformer [ 4 4 , 5 5 ]. Being advantageous over conventional line-frequency transformers [ 6 6 , 7 7 ] in its compact structure, low stored energy, excellent transient response, high efficiency, good fault tolerance and high reliability, PICT is promising to be used in DC power supply below 1 MV. PICT is driven by switching power supply and generally its magnetic core is made of ferrite. Secondary coils are arranged as tracks on printed circuit boards (PCB). Plurality of PCB stacks are connected in series so that output stage can generate a DC voltage in excess of 100 kV and a current of 50–200 mA. Figure 1(a) Figure 1(a) shows schematically an experimental PICT implementation we developed. Energized by a 33 kHz AC signal generated by pulse width modulated inverter, the PICT has 5 turns in primary windings, and comprises 27 PCB stacks. Each PCB circuit contains 32 identical secondary modules, and each module consists of 2 turns of secondary coils and a full wave bridge rectifier ( Fig. 1(b) Fig. 1(b) ). Assuming no losses, when excited by an excitation signal of amplitude U P , the output DC voltage U DC is: <math display="block" id="M1"><mrow><msub><mi>U</mi><mrow><mtext>DC</mtext></mrow></msub><mo>=</mo><mn>2</mn><mfrac><mrow><msub><mi>N</mi><mn>2</mn></msub></mrow><mrow><msub><mi>N</mi><mn>1</mn></msub></mrow></mfrac><msub><mi>U</mi><mtext>P</mtext></msub><mo>=</mo><mn>2</mn><mfrac><mrow><mn>32</mn><mo>×</mo><mn>27</mn><msub><mi>n</mi><mn>2</mn></msub></mrow><mrow><msub><mi>N</mi><mn>1</mn></msub></mrow></mfrac><msub><mi>U</mi><mtext>P</mtext></msub><mn>,</mn></mrow></math> where N 1 and N 2 are the number of turns in primary and secondary windings, respectively; and n 2 is the number of turns in each secondary module. Sized at just Φ 500 mm×600 mm, the PICT works at U P =520 V in a tank filled with SF6. According to Eq.(1), it shall output a DC voltage of over 300 kV. However, from open-loop experiments, we had U P =400 V and U DC =220 kV in the no-load test; with the load, we had U P =200 V and U DC =100 kV at output current of 15 mA, due to limited power of the front-end power supply. II. THEORETICAL ANALYSIS OF MAGNETIC FLUX LEAKAGE IN PICT 1 The measured DC output of the PICT exhibited a severe drop compared to theoretical value, and magnetic leakage flux (MFL) was considered as an essential reason. To isolate associated ferrite tiles from neighboring magnetic core, adjacent PCB stacks were isolated by insulating films of low magnetic conductivity μ to form gaps in the magnetic circuit. MFL occurred at fringes of gaps in form of "by-pass" flux, as a result the upper section of the magnetic core carried less flux. Figure 2 Figure 2 is a schematic diagram of insulating film and by-pass flux. Number the 27 PCB stacks as m 1 , m 2 , ⋯ , m N , ⋯ , m 27 from bottom to top. The 28 magnetic gaps introduced by 27 isolation layers give rise to flux leakage Δ Φ , which is proportional to the main flux Φ of that position [ 8 8 , 9 9 ], i.e.: Δ . Δ Φ makes K N < 1, where K N is the magnetic coupling efficiency in the N th PCB. So the output voltage U N determined by K N decreases along the vertical: <math display="block" id="M2"><mrow><msub><mi>U</mi><mi>N</mi></msub><mo>=</mo><msub><mi>U</mi><mn>0</mn></msub><mo>⋅</mo><msub><mi>K</mi><mi>N</mi></msub><mtext> </mtext><mtext> </mtext><mo stretchy="false">(</mo><mn>0</mn><mo><</mo><msub><mi>K</mi><mi>N</mi></msub><mo><</mo><mn>28,</mn><mtext> </mtext><mn>0</mn><mo><</mo><mi>N</mi><mo><</mo><mn>28</mn><mo stretchy="false">)</mo><mn>,</mn></mrow></math> where, K N is mainly up to the width of gap, i.e. thickness of insulating films. Therefore, the MFL causes voltage losses through reducing K N of the upper stages. The MFL-caused leakage inductance in the equivalent circuit is shown in Fig. 3 Fig. 3 , where T = 5:2 is the ratio of coupling inductance; the subscripts L, P and S denote the load resistance, primary coil and secondary coil, respectively; L kp and L ks are the leakage inductance; and C P and C S are the stray capacitance. In the no-load test, the R L branch was a high impendence path, so L kp and L ks formed with C S a series resonant circuit and did not reduce the voltage across R L . When the current flowing through R L became mA level, electric resonance would disappear, by then the voltage would be allocated to leakage inductance and R L voltage will reduce. MFL is often a significant single factor in degrading the performance of PICT. It not only leads to voltage drop but also break the voltage uniformity between PCB stacks. So it is necessary to figure out the value of K N and then manage to compensate it. Our early studies [ 10 10 , 11 11 ] with a preliminary no-load test on a primitive PICT apparatus comprising 5 PCB cards showed different properties from reality. To study the characteristics of MFL in load operation, finite element simulation and experiments were carried out. III. MAGNETIC FIELD ANALYSIS USING CST 1 Theoretically, by analyzing magnetic field energy contained in the transformer windings [ 12 12 , 13 13 ], leakage flux can be calculated, but it is only suitable for qualitative analysis. Finite elements analysis is more applicable to numerical analysis. Using CST FEM studio, we performed magnetic field simulation of the PICT. In the model, the primary windings have 5 turns, and the exciting current is 50 A. The cross section of magnetic core is 0.01 m 2 . The relative permeability μ 0 is 2400 and the gap width is 0.15 mm. The mesh number is 6d5, and the computational accuracy is d-6. CST gives the magnetic field density B in model space. The results are shown in Fig. 4 Fig. 4 . The by-pass flux is the foremost source of leakage flux. Integrating B across the 27 PCB sections to get magnetic flux Φ , we had the magnetic flux data of 27 PCB stacks gapped 0.15 mm, as shown in Fig. 5 Fig. 5 . The Φ curve is close to an exponential distribution, being Φ 1 =7.791×10 -4 Wb for the bottom planar and Φ 27 = 6.672×10 -4 Wb for the top planar. In the simulation B =800 Gs, so theoretically Φ should be 8.0×10 -4 Wb. It can be calculated K 1 =0.974 and K 27 =0.834. Figure 5 Figure 5 shows also simulation results of 0.1- and 0.3-mm gap widths, with K 1 =0.980 and K 27 = 0.887 at 0.1-mm gap width, while K 1 =0.944 and K 27 = 0.740 at 0.3-mm gap width. As discussed above, the gap width is the most significant factor affecting the leakage flux, and using thinner insulating films is beneficial to lessen leakage flux. IV. EXPERIMENTAL PHENOMENON 1 Tests with and without load were performed. To measure DC output voltage of all PCB stacks, in each PCB the input terminals were grounded and output ports were connected to load resistance R L . The insulating films are 0.15 mm thick. In the load test, R L =120 kΩ and the load current was 7 mA; while in no-load test, R L =1000 MΩ. Figure 6(a) Figure 6(a) shows the voltage curve. The bottom PCB output was 824 V and the top one was 704 V in the load test, with a 14.6% drop. By contrast, the no-load output values were quite similar. The two curves show a broad distinction consistent with theoretical analysis. According to repeated tests, the drop between the bottom and top PCB was 13%–17%, showing a good coincidence with CST simulation. Figure 6(b) Figure 6(b) shows the experimental results and the CST simulation. Conclusively, in load operation of the PICT, MFL causes a lower generated voltage on the upper PCB stacks and reduces voltage efficiency. And a numerical basis for PICT design can be provided by accurate CST calculation of the magnetic field. V. COMPENSATION TO FLUX LEAKAGE 1 After obtaining the value of leakage flux, which working as leakage inductance in equivalent circuit, we managed to compensate it. The method of winding more secondary coils proposed in Ref. [ 3 3 ] is not suitable to PICT. A more practical alternative is to connect suitable compensation capacitor across the secondary coil [ 10 10 , 11 11 , 14 14 - 16 16 14-16 ]. We calculated and optimized the value of compensation capacitor using Multisim. To make DC voltage of the upper PCB stacks of low K N output similar to the bottom ones, 33 nF capacitor is required in our PICT apparatus. What noteworthy is that the capacitances in different PCB stacks are nearly equal. To evaluate performance of the compensation capacitor, Multisim simulation over three individual secondary modules of different K N was carried out. The simulation circuit is the same as circuit shown in Fig. 2 Fig. 2 . The three coupling inductances were T 1 , T 2 and T 3 , where the coupling efficiency of T 1 was 0.8, representing the top PCB; the coupling efficiency of T 2 was 0.9, representing the intermediate PCB; and the coupling efficiency of T 1 was 0.98, representing the bottom PCB. The compensation capacitors across the secondary coil were 33 nF. Figure 7 Figure 7 shows the output voltage before and after compensation, where the red, green and blue lines are outputs of T 1 , T 2 and T 3 , respectively. The three outputs are distinct before compensation, while after compensation they are pretty much the same, in a higher value than before. To verify above simulation, 2.2 nF and 33 nF capacitors were installed in the topmost PCB and DC voltages were measured. The results are given in Table 1 Table 1 . The 33 nF capacitor made voltage generation being equally distributed between PCB stacks, while other two did not. All these demonstrate that proper capacitance selection of the compensation capacitor is an effective and satisfactory way to improve magnetic leakage of the PICT. 1 2 Value of capacitor 1 2 Bottommost PCB (V) 2 1 Topmost PCB 1 1 No compensation 1 1 Compensated 1 1 0.0 1 1 552 1 1 470 1 1 470 1 1 2.2 1 1 550 1 1 470 1 1 473 1 1 33.0 1 1 556 1 1 472 1 1 570 VI. CONCLUSION 1 In this paper MFL in PICT is studied and proved to be a significant factor causing voltage drop. CST calculation is introduced, and the comparison between experiment and simulation results indicate that CST can describe MFL clearly by quantitative calculation. Compensation capacitor is used to minimize leakage inductance in load test and the desired results are achieved through experimental verification. This research has scientific and applied significance for the construction of new style of high-power DC source. References J D Cross . US Patent 5631815 , High voltage power supply , 1997 . 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