Research into the sampling methods of digital beam position measurement

Research into the sampling methods of digital beam position measurement 1 first-author 1 corresp Corresponding author, zlei@ustc.edu.cn Corresponding author, zlei@ustc.edu.cn zlei@ustc.edu.cn 1 1 1 State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China A fully digital beam position monitoring system (DBPM) has been designed for SSRF (Shanghai Synchrotron Radiation Facility). As analog-to-digital converter (ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is studied, too. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn (TBT) position resolution better than 1 μm is achieved, and the slow-acquisition (SA) position resolution is improved from 4.28 μm to 0.17 μm. Beam position monitor Analog-digital conversion Digital phase-locked loop Interleaved distribution scheme I. INTRODUCTION 1 Beam position monitors (BPMs) form an indispensable system of a synchrotron radiation source [ 1 1 - 6 6 1-6 ]. It measures the transverse centroid of the beam in the storage ring and the linac, the linac-to-booster transfer line, the full energy booster, and the booster-to-storage ring transfer line [ 7 7 ]. A digital BPM (DBPM) system was designed for Shanghai Synchrotron Radiation Facility (SSRF), a third generation light source and an important platform in various scientific research domains [ 1 1 , 5 5 , 6 6 ]. Figure 1 Figure 1 shows its block diagram. It receives signals from four capacitive pickup electrodes positioned around the beam pipe. The buttons generate fast pulses at the electron bunch repetition rate of f RF =499.654 MHz [ 1 1 ]. The input signals are first conditioned by the analogue radio frequency (RF) circuits in four sampling channels of the DBPM, with band-pass filters and amplification circuits. Using RF amplifiers and attenuators, a dynamic range of over 50 dB is achieved [ 6 6 ]. Then, the 499.654 MHz RF signals are digitized by four 14-bit ADCs with a sampling rate of 117.28 MHz, through which digital intermediate frequency (IF) signals of 30.5 MHz are generated. The digital IF signals are further processed by the algorithms integrated within a field-programmable gate array (FPGA) device. As shown in Fig. 2 Fig. 2 , the IF signals are converted into I and Q arrays by digital down converters (DDCs) before the amplitudes of four input signals are calculated by the Cordic algorithm. Then, by employing the Δ/∑ principle [ 8 8 ], the beam position can be calculated using Eqs. (1) and (2) <math display="block" id="M1"><mrow><mi>X</mi><mo>=</mo><msub><mi>K</mi><mi>x</mi></msub><mfrac><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>−</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>−</mo><msub><mi>V</mi><mn>4</mn></msub></mrow><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>+</mo><msub><mi>V</mi><mn>4</mn></msub></mrow></mfrac><mn>,</mn></mrow></math> <math display="block" id="M2"><mrow><mi>Y</mi><mo>=</mo><msub><mi>K</mi><mi>y</mi></msub><mfrac><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>−</mo><msub><mi>V</mi><mn>3</mn></msub><mo>−</mo><msub><mi>V</mi><mn>4</mn></msub></mrow><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>+</mo><msub><mi>V</mi><mn>4</mn></msub></mrow></mfrac><mn>,</mn></mrow></math> where, K x = K y =10 cm are the effective length factors in X and Y directions, and V 1-4 are amplitudes of signals in four RF channels. Harmonic number of the SSRF storage ring is H = 720, so the turn rate is given by the machine clock frequency ( f mc ) 499.654 MHz /H = 693.964 kHz. Using a low-pass-filter (LPF), the slow-acquisition (SA) data are obtained from turn-by-turn (TBT) data. While the TBT data are used to analyze the beam position spectrum and study the position noise between tens of kHz to hundreds of kHz, the SA data is applied to beam monitoring, with a feedback loop to stabilize the beam orbit [ 7 7 ]. Performance of the ADCs affects measurement resolution of the overall BPM system, so great care must be taken with the sampling method. In this study, we explored the synchronization and the off-tune sampling modes, in the electronics design, which was evaluated through tests. A digital phase-locked loop (DPLL) algorithm was deployed on an FPGA device, enabling the system to implement and switch between different sampling methods used by the ADCs. To address the issue of long-term stability of the ADCs and the RF circuits, a switch array was designed to implement interleaved distribution of the input signals among four sampling channels. Results of on-site tests with different sampling methods were compared. II. SAMPLING METHODS IN THE ADCS 1 The electron bunches produce RF signals in the BPM pick-ups with a frequency of f RF = 499.654 MHz, which are fed into the DBPM inputs. The signals are modulated by a macro pulse due to the turn frequency given by f mc = 693.964 kHz ( f RF / H ). If the ADC sampling clock was not synchronized to the machine clock ( f mc ), there would be a variation in the number of RF signals per TBT cycle [ 6 6 ]. This variation would cause undue fluctuations in the amplitude measurements, which could finally deteriorate the position resolution. Therefore, the synchronization sampling becomes mandatory for the TBT data, which means the sampling frequency ( f s ) should be an integer multiple of f mc , as shown in Eq. (3). In such case, the TBT data rate is exactly equivalent to f mc , <math display="block" id="M3"><mrow><msub><mi>f</mi><mrow><mtext>in</mtext></mrow></msub><mo>/</mo><msub><mi>f</mi><mtext>s</mtext></msub><mo>=</mo><mn>720</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mo stretchy="false">(</mo><mn>169</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo stretchy="false">)</mo><mo>=</mo><mn>720</mn><mo>/</mo><mn>169.</mn></mrow></math> Regarding the SA data, the requirement on the sampling frequency is quite different. As mentioned previously, the TBT data (694 kHz) is filtered by a digital LPF to obtain the SA data with a much lower rate of 10 Hz; therefore, if the sampling clock is not synchronized to the machine clock, the amplitude fluctuation can be filtered out. On the other hand, due to modulation of the macro pulse, sidebands with a frequency interval of f mc exist in the frequency spectrum of the digital IF signal. In the ADCs, the circuit non-linearity causes harmonics of the digital IF signal to appear, which is accompanied by a similar distribution of sidebands. Some of the sidebands around the harmonics would overlap at the digital IF signal frequency (44 f mc ), which would cause measurement errors with a very low frequency. This was observed in the SA measurement results of some BPM instrumentations, such as Libera Electron [ 9 9 ]. To address this issue, we should shift f s in Eq. (3) by a certain small frequency difference Δ f to relocate the sideband of the harmonics outside of the pass-band (5 Hz) of the LPF for the SA data [ 9 9 ]. A straightforward idea is to set f s totally independent from f mc , but the problem is that Δ f cannot be controlled precisely as f mc shifts along with time. In this paper, we use an off-tune sampling mode, in which Δ f is set to a certain value that can be modified easily by commands. To accommodate the above sampling modes and switch between them, a DPLL is specially designed based on an FPGA device. III. SYNCHRONIZATION AND OFF-TUNE SAMPLING BASED ON DPLL 1 In conventional methods for clock synchronization, commercially available PLL chips are employed, which consist of a phase detector, a charge pumper, and a loop filter implemented in ICs. This is an easy way to design sampling clock generation circuits, however, rendering it impossible to switch between different sampling modes. To achieve good flexibility, we adopted a digital solution based on a modified DPLL in an FPGA device (XC4VFX100-11ff1152 from Xilinx virtex-4 family). The output codes from the DPLL are used to control an external digital-to-analog convertor (DAC) whose output is further fed to a voltage-controlled crystal oscillator (VCXO), as shown in Fig. 3 Fig. 3 . With different division factors ( M and N in Fig. 3 Fig. 3 ), the frequency relationship between the output clock ( f s ) and the input reference clock ( f mc ) can be determined. As a kernel parts in DPLL, the digital phase detector is categorized into the linear type like Hogge phase detector and the nonlinear type like Alexander phase detector (i.e. Bang-Bang phase detector) [ 10 10 , 11 11 ]. Alexander phase detector is chosen in the DBPM system, considering its superior performance and simplicity [ 12 12 ]. It outputs 3-bit data indicating which one of the two input signals leads the other. Its structure and principle are shown Fig. 4 Fig. 4 , where A, T and B are three samples taken by three consecutive clock edges. If CLK2 leads CLK1, the first sample (A) is unequal to the last two (T and B). We implemented this digital phase detector in the FPGA, and conducted simulations based on ISim (ISE 14.4). The results agree well with theoretical analysis ( Fig. 5 Fig. 5 ). Connecting this phase detector with the loop filter and other components in Fig. 3 Fig. 3 implements a whole DPLL. With this scheme, there exists a relationship between the frequencies of two input clocks of the DPLL in the locked state, as shown in Eq. (4): <math display="block" id="M4"><mrow><msub><mi>f</mi><mrow><mtext>clk2</mtext></mrow></msub><mo>=</mo><mn>2</mn><msub><mi>f</mi><mrow><mtext>clk1</mtext></mrow></msub><mn>.</mn></mrow></math> Considering the relationship among the machine clock, the ADC sampling clock, CLK1 and CLK2 in Fig. 3 Fig. 3 , f s can be expressed as Eq. (5). Then the relationship in Eq. (3) can be achieved with M =338 and N =1, <math display="block" id="M5"><mrow><msub><mi>f</mi><mtext>s</mtext></msub><mo>=</mo><mi>M</mi><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mo stretchy="false">(</mo><mn>2</mn><mi>N</mi><mo stretchy="false">)</mo><mn>.</mn></mrow></math> Meanwhile, as mentioned above, to prevent the sidebands of harmonics from deteriorating the SA data, f s should be shifted by a certain frequency difference Δ f (i.e. the off-tune sampling mode). In this design, we implemented Δ f by configuring a frequency divider with a factor K , <math display="block" id="M6"><mrow><mi>K</mi><mo>=</mo><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mi>Δ</mi><mi>f</mi><mn>.</mn></mrow></math> Thus, in the off-tune sampling mode, f s can be expressed as <math display="block" id="M7"><mrow><msub><mi>f</mi><mtext>s</mtext></msub><mo>=</mo><mn>169</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>+</mo><mi>Δ</mi><mi>f</mi><mo>=</mo><mn>169</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>+</mo><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mi>K</mi><mo>=</mo><mo stretchy="false">(</mo><mn>169</mn><mi>K</mi><mo>+</mo><mn>1</mn><mo stretchy="false">)</mo><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mi>K</mi><mn>.</mn></mrow></math> Comparing Eq. (5) with Eq. (7), the off-tune sampling can be implemented by the DPLL, and the relationships among N , M and K are described by Eq. (8): <math display="block" id="M8"><mrow><mi>N</mi><mo>=</mo><mi>K</mi><mo>/</mo><mn>2,</mn><mtext> </mtext><mi>M</mi><mo>=</mo><mn>169</mn><mi>K</mi><mo>+</mo><mn>1.</mn></mrow></math> The next step is to determine the Δ f value. The major influence comes from the sideband (44 f mc ) of the third harmonic (37 f mc ) overlapping on the digital IF signal [ 9 9 ]. As shown in Fig. 6 Fig. 6 , in the off-tune sampling mode, the sideband of the third harmonic and the digital IF signal are shifted by 12Δ f and -4Δ f , respectively, i.e. a total frequency interval of 16Δ f is achieved. To guarantee that the sideband can be effectively suppressed by the LPF (5 Hz pass band) for the SA data, the value of Δ f should meet the requirement as follows: <math display="block" id="M9"><mrow><mn>16</mn><mi>Δ</mi><mi>f</mi><mo>></mo><mn>5.</mn></mrow></math> Meanwhile, considering the frequency tuning range of the VCXO (VFVX 120), the upper limitation of Δ f is <math display="block" id="M10"><mrow><mi>Δ</mi><mi>f</mi><mo><</mo><mn>5.85.</mn></mrow></math> Combining Eqs. (9), (10) and (6), one obtains that the K value ranges from 118 to 2221, <math display="block" id="M11"><mrow><mn>5</mn><mo>/</mo><mn>16</mn><mo><</mo><mi>Δ</mi><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mi>K</mi><mo><</mo><mn>5.85</mn><mo>→</mo><mn>118</mn><mo><</mo><mi>K</mi><mo><</mo><mn>2221.</mn></mrow></math> In the design of DPLL, K is chosen as 256, and the corresponding values of N and M are 128 and 43265. The final sampling frequency in the off-tune mode can be expressed as <math display="block" id="M12"><mrow><mtable columnalign="left"><mtr columnalign="left"><mtd columnalign="left"><mrow><msub><mi>f</mi><mtext>s</mtext></msub></mrow></mtd><mtd columnalign="left"><mrow><mo>=</mo><mi>M</mi><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mo stretchy="false">(</mo><mn>2</mn><mi>N</mi><mo stretchy="false">)</mo></mrow></mtd></mtr><mtr columnalign="left"><mtd columnalign="left"><mrow/></mtd><mtd columnalign="left"><mrow><mo>=</mo><mn>43265</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mo stretchy="false">(</mo><mn>2</mn><mo>×</mo><mn>128</mn><mo stretchy="false">)</mo></mrow></mtd></mtr><mtr columnalign="left"><mtd columnalign="left"><mrow/></mtd><mtd columnalign="left"><mrow><mo>=</mo><mn>169</mn><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>+</mo><msub><mi>f</mi><mrow><mtext>mc</mtext></mrow></msub><mo>/</mo><mn>256.</mn></mrow></mtd></mtr><mtr columnalign="left"><mtd columnalign="left"><mrow/></mtd><mtd columnalign="left"><mrow/></mtd></mtr></mtable></mrow></math> IV. CONSIDERATION OF LONG-TERM STABILITY 1 In the DBPM, the SA data are mainly used to monitor long term variation of the beam position [ 7 7 ]. The beam position is calculated from the input signal amplitudes ( A 1 , A 2 , A 3 , A 4 ) multiplied by the gains of four sampling channels ( G 1 , G 2 , G 3 , G 4 ), as shown in Eqs. (13) and (14): <math display="block" id="M13"><mrow><mtable columnalign="left"><mtr columnalign="left"><mtd columnalign="left"><mi>X</mi></mtd><mtd columnalign="left"><mrow><mo>=</mo><msub><mi>K</mi><mi>x</mi></msub><mo>∗</mo><mfrac><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>−</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>−</mo><msub><mi>V</mi><mn>4</mn></msub></mrow><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>+</mo><msub><mi>V</mi><mn>4</mn></msub></mrow></mfrac></mrow></mtd></mtr><mtr columnalign="left"><mtd columnalign="left"><mrow/></mtd><mtd columnalign="left"><mrow><mo>=</mo><msub><mi>K</mi><mi>x</mi></msub><mo>∗</mo><mfrac><mrow><msub><mi>G</mi><mn>1</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>1</mn></msub><mo>−</mo><msub><mi>G</mi><mn>2</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>2</mn></msub><mo>+</mo><msub><mi>G</mi><mn>3</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>3</mn></msub><mo>−</mo><msub><mi>G</mi><mn>4</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>4</mn></msub></mrow><mrow><msub><mi>G</mi><mn>1</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>1</mn></msub><mo>+</mo><msub><mi>G</mi><mn>2</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>2</mn></msub><mo>+</mo><msub><mi>G</mi><mn>3</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>3</mn></msub><mo>+</mo><msub><mi>G</mi><mn>4</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>4</mn></msub></mrow></mfrac><mn>,</mn></mrow></mtd></mtr></mtable></mrow></math> <math display="block" id="M14"><mrow><mtable columnalign="left"><mtr columnalign="left"><mtd columnalign="left"><mi>Y</mi></mtd><mtd columnalign="left"><mrow><mo>=</mo><msub><mi>K</mi><mi>y</mi></msub><mo>∗</mo><mfrac><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>−</mo><msub><mi>V</mi><mn>3</mn></msub><mo>−</mo><msub><mi>V</mi><mn>4</mn></msub></mrow><mrow><msub><mi>V</mi><mn>1</mn></msub><mo>+</mo><msub><mi>V</mi><mn>2</mn></msub><mo>+</mo><msub><mi>V</mi><mn>3</mn></msub><mo>+</mo><msub><mi>V</mi><mn>4</mn></msub></mrow></mfrac></mrow></mtd></mtr><mtr columnalign="left"><mtd columnalign="left"><mrow/></mtd><mtd columnalign="left"><mrow><mo>=</mo><msub><mi>K</mi><mi>y</mi></msub><mo>∗</mo><mfrac><mrow><msub><mi>G</mi><mn>1</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>1</mn></msub><mo>+</mo><msub><mi>G</mi><mn>2</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>2</mn></msub><mo>−</mo><msub><mi>G</mi><mn>3</mn></msub><mo>∗</mo><mi>A</mi><mn>3</mn><mo>−</mo><msub><mi>G</mi><mn>4</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>4</mn></msub></mrow><mrow><msub><mi>G</mi><mn>1</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>1</mn></msub><mo>+</mo><msub><mi>G</mi><mn>2</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>2</mn></msub><mo>+</mo><msub><mi>G</mi><mn>3</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>3</mn></msub><mo>+</mo><msub><mi>G</mi><mn>4</mn></msub><mo>∗</mo><msub><mi>A</mi><mn>4</mn></msub></mrow></mfrac><mn>,</mn></mrow></mtd></mtr></mtable></mrow></math> where K x = K y =10 cm are the effective length factors in X and Y directions; G 1-4 are the gain of the sampling channels; and A 1-4 are amplitude of the input signals. In the ideal situation, the four gain factors are equal and there are no measurement errors in beam position results; however, it is not the case in real applications. If the difference among the four gain factors keeps constant, the measurement error in SA data can easily be corrected by off-line calibration. However, we found that these gain factors change quite differently, which would inevitably deteriorate the resolution of the SA data in long term. As shown in Fig. 7 Fig. 7 , fluctuation of the SA data are obvious (the corresponding position resolution is 0.832 μm) in the laboratory tests where the input signals were generated by a signal sources (ROHDE & SCHWARZ SMA 100A). Therefore, we must apply new methods to address this issue. The basic idea is to distribute the four input signals to the four sampling channels alternately according to a specified sequence. We designed an interleaved distribution scheme by using an RF switch array with the structure shown in Fig. 8(a) Fig. 8(a) [ 13 13 ]. With different controlling signals, this switch array establishes corresponding signal paths between the four input ports and the four sampling channels. The controlling signals are generated by the FPGA, and are organized in a special sequence, with which the four input signals are evenly interleaved to four channels, as shown in Fig. 8(b) Fig. 8(b) . The switching frequency is designed as 5.42 kHz, which is much larger than the pass band (5 Hz) of the LPF for the SA data in Fig. 2 Fig. 2 . So the distortion introduced by the switching process can easily be filtered out. In this case, the four sampling channels have equivalent influence on the processing of each input signal, which means the equality of effective gains for all input signals, i.e. the measurement errors caused by the long term fluctuation of electronics are greatly suppressed. Results of initial tests conducted in laboratory are shown in Fig. 9 Fig. 9 . The position information of the SA data in 30 min is stable and the resolution is 0.032 μm, rather than 0.832 μm in Fig. 7 Fig. 7 . V. TEST RESULTS 1 To evaluate overall performance of the DBPM in different sampling methods, we conducted commissioning tests in SSRF ( Fig. 10 Fig. 10 ). The modulated RF signals from pickups were sent to the DBPM through four coaxial cables. After manipulating the signals, the DBPM sent the beam position information to a remote PC through ethernet for further analysis. A. Results of the TBT data 2 We tested the TBT data in two modes: the synchronization sampling and the off-tune sampling. The normalized signal amplitudes of the TBT data in both sampling modes are shown in Fig. 11 Fig. 11 . Fluctuation can be clearly observed in Fig. 11(b) Fig. 11(b) , just as discussed in Sec. II. Therefore, the synchronization sampling is chosen for the TBT data, and the position resolution is around 0.61 μm. B. Results of the SA data 2 As shown in Fig. 12 Fig. 12 , the interleaved distribution scheme we designed can improve performance of the SA data significantly; the position resolution of a 30-min data collection test could be enhanced from 4.28 μm to 0.17 μm. And similar performance can be achieved in the synchronization sampling and the off-tune sampling, as shown in Figs. 12(b) and 12(c) Figs. 12(b) and 12(c) . This is probably due to the good performance of the analog front-end in the DBPM system. VI. CONCLUSION 1 Different kinds of sampling methods are studied to optimize the performance of the DBPM designed for SSRF, including the synchronization sampling, the off-tune sampling and the interleaved distribution scheme which aims to address the long term stability. The commissioning test results in SSRF indicate that with an optimized sampling method, a TBT position resolution is better than 1 μm. It was found that the SA resolution can be effectively enhanced to 0.17 μm using an interleaved distribution scheme. Both the position resolutions of the TBT and the SA data exceed the technical requirements. References S Y Chen , H J Xu , Z T Zhao , et al . Shanghai synchrotron radiation facility . Proceeding of the Particle Accelerator Conference , 1999 , 1 : 209 - 211 . DOI: 10.1109/PAC.1999.795666 http://doi.org/10.1109/PAC.1999.795666 Shanghai synchrotron radiation facility X Yi , Y B Leng , L W Lai , et al . RF front-end for digital beam position monitor signal processor . Nucl Sci Tech , 2011 , 22 : 65 - 69 . RF front-end for digital beam position monitor signal processor L W Lai , B Leng Yong , X Yi , et al . DBPM signal processing with field programmable gate arrays . Nucl Sci Tech , 2011 , 22 : 129 - 133 . DBPM signal processing with field programmable gate arrays X D Sun and Y B Leng . Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA . Nucl Sci Tech , 2014 , 25 : 020401 . DOI: 10.13538/j.1001-8042/nst.25.020401 http://doi.org/10.13538/j.1001-8042/nst.25.020401 Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA H Zhou , S B Liu , L Zhao , et al . Design of the fully digital beam position monitor for beam position measurement in SSRF . 9th International Conference on Electronic Measurement & Instruments , 2009 , 1 : 1045 - 1051 . DOI: 10.1109/ICEMI.2009.5273995 http://doi.org/10.1109/ICEMI.2009.5273995 Design of the fully digital beam position monitor for beam position measurement in SSRF Y Han , L Zhao , S B Liu , et al . A beam position measurement system of fully digital signal processing at SSRF . Nucl Sci Tech , 2012 , 23 : 75 - 82 . A beam position measurement system of fully digital signal processing at SSRF Y B Leng , W M Zhou , Y Z Chen , et al . Beam instrumentation system development and commissioning in SSRF . Proceedings of European Particle Accelerator Conference , Genoa, Italy , 2008 . Beam instrumentation system development and commissioning in SSRF G Vismara . The comparision of signal processing systems for beam position monitors . Proceedings of the 4th European Workshop on Diagnostics and Instrumentation for Particle Accelerators DIPAC 99 , Chester, England , IT05 , 1999 . The comparision of signal processing systems for beam position monitors Y B Yan . Research of SSRF BPM data acquisition system and preliminary application. Ph.D. Thesis , Shanghai Institute of Applied Physics, Chinese Academy of Sciences , 2009 , 60 - 63 . (in Chinese) Research of SSRF BPM data acquisition system and preliminary application. Ph.D. Thesis Jr C R Hogge . A self correcting clock recovery circuit . J Lightwave Technol , 1985 , 3 : 1312 - 1314 . DOI: 10.1109/JLT.1985.1074356 http://doi.org/10.1109/JLT.1985.1074356 A self correcting clock recovery circuit J D H Alexander . Clock recovery from random binary data . Electron Lett , 1975 , 11 : 541 - 542 . DOI: 10.1049/el:19750415 http://doi.org/10.1049/el:19750415 Clock recovery from random binary data XILINX , XAPP854 (v1.0). Digital phase-locked loop (DPLL) reference design , Oct. 10, 2006 . http://www.xilinx.com/support/documentation/application_notes/xapp854.pdf http://www.xilinx.com/support/documentation/application_notes/xapp854.pdf XAPP854 (v1.0). Digital phase-locked loop (DPLL) reference design Libera Electron User Manual 2.04. Instrumentation Technologies , 2009 . Libera Electron User Manual 2.04. Instrumentation Technologies The authors would like to thank all of the SSRF collaborators who helped this paper possible. 10.13538/j.1001-8042/nst.26.030402 Supported by the Knowledge Innovation Program of the Chinese Academy of Sciences (No. KJCX2-YW-N27) and National Natural Science Foundation of China (Nos. 11205153 and 11175176) 2014-05-05 2014-10-13 2015-06-20 2015-06-20 2021-04-11 2015 Nuclear Science and Techniques 3 26