Heavy-ion and pulsed-laser single event effects in 130-nm CMOS-based thin/thick gate oxide anti-fuse PROMs

Heavy-ion and pulsed-laser single event effects in 130-nm CMOS-based thin/thick gate oxide anti-fuse PROMs 1 2 first-author equal 1 2 3 first-author equal 4 1 2 corresp Corresponding author: j.liu@impcas.ac.cn. Corresponding author: j.liu@impcas.ac.cn. j.liu@impcas.ac.cn 5 4 1 2 1 2 1 1 2 1 2 Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China University of Chinese Academy of Sciences, Beijing 100049, China University of Chinese Academy of Sciences, Beijing 100049, China School of Physical Science and Technology, Lanzhou University, Lanzhou 730000, China School of Physical Science and Technology, Lanzhou University, Lanzhou 730000, China Academy of Shenzhen State Microelectronic Co., Ltd., Shenzhen 518004, China Academy of Shenzhen State Microelectronic Co., Ltd., Shenzhen 518004, China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, Guangzhou 510610, China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, Guangzhou 510610, China Single event effects of 1-T structure programmable read-only memory (PROM) devices fabricated with a 130-nm complementary metal oxide semiconductor (CMOS)-based thin/thick gate oxide anti-fuse process were investigated using heavy ions and a picosecond pulsed laser. The cross sections of a single event upset (SEU) for radiation-hardened PROMs were measured using a linear energy transfer (LET) ranging from 9.2 to 95.6 MeV·cm 2 ·mg -1 . The result indicated that the LET threshold for a dynamic bit upset was ~9 MeV·cm 2 ·mg -1 , which was lower than the threshold of ~20 MeV·cm 2 ·mg -1 for an address counter upset owing to the additional triple-modular-redundancy structure present in the latch. In addition, a slight hard error was observed in the anti-fuse structure when employing 209 Bi ions with extremely high LET values (~91.6 MeV·cm 2 ·mg -1 ) and large ion fluence (~1 × 10 8 ions·cm -2 ). To identify the detailed sensitive position of an SEU in PROMs, a pulsed laser with a 5-μm beam spot was used to scan the entire surface of the device. This revealed that the upset occurred in the peripheral circuits of the internal power source and I/O pairs rather than in the internal latches and buffers. This was subsequently confirmed by a 181 Ta experiment. Based on the experimental data and a rectangular parallelepiped (RPP) model of the sensitive volume, the space error rates for the used PROMs were calculated using the CRÈME-96 prediction tool. The results showed that this type of PROM was suitable for specific space applications, even in the geosynchronous orbit. Anti-fuse PROM Single event effects Heavy ions Pulsed laser Space error rate 1 Introduction 1 Programmable read only memory (PROM), as a one-time write memory, is one of the most stable and reliable devices for data storage. Thus, it has been used extensively in space electronic equipment over the past several decades. PROMs with good radiation tolerance to high-energy cosmic rays are ideal media to store the original code of electronic systems, for example, as the configuration memory for field programmable gate array (FPGA) devices [ 1 1 – 3 3 1–3 ]. In such situations, any error in the PROMs may cause erroneous configurations of the target chip and threaten the normal operation of space vehicles in orbit. In general, the memory cells of PROMs have a natural radiation resistance owing to their unique fabrication processes such as the oxide-nitride-oxide anti-fuse, amorphous silicon anti-fuse, and gate oxide anti-fuse [ 4 4 – 6 6 4–6 ]. Previous studies on single event effects (SEE) of PROMs verified that the memory cells of PROMs manufactured by the micron and submicron processes are almost immune to upset and latch-up [ 1 1 , 2 2 , 7 7 ]. However, the readout and control circuits rather the storage elements seem to be very susceptible to SEE because of their CMOS technologies. In [ 1 1 , 2 2 ], at least seven ion-induced errors were observed in peripheral circuits, including dynamic upsets, address errors, and functional interrupts. This showed that the critical procedure for designing a PROM with high radiation tolerance involves effectively mitigating and evaluating the SEE sensitivity of peripheral circuits. Although the error types and mechanisms of SEEs in PROMs were analyzed in [ 1 1 , 2 2 ], there is no report that identifies the sensitive positions of the PROM’s peripheral circuits as directly based on a positioning irradiation experiment. Moreover, with the feature size scaled down to the deep-submicron or even the nanometer level, a PROM with high density and large capacity was developed in recent years. Considering its wide application prospects in space electronics, the radiation response of these new-type PROMs should be characterized in depth. In this paper, the SEEs of 1-T-structure PROMs fabricated with a 130-nm CMOS-based thin/thick gate oxide anti-fuse process are analyzed by heavy ions and a pulsed laser. The thin/thick gate oxide anti-fuse technology is simple and compatible with traditional CMOS processes. This provides a possibility of both decreasing the area of the memory cell and increasing the read speed and storage capacity of the device. In previous works, it was demonstrated that bulk silicon epitaxy and deep well processes are effective in mitigating the SEEs for this type of PROM in 180-nm and 130-nm processes [ 8 8 , 9 9 ]. Furthermore, this paper focuses on conducting a systematical study of SEEs in 130-nm CMOS-based PROM devices. The study includes a heavy ion test, pulsed-laser mapping experiment, and space error rate prediction. In detail, error types such as the dynamic bit upset and address counter upset, the effectiveness of error detection and correction (EDAC)- and triple modular redundancy (TMR)-hardened strategies, the heavy ion response of anti-fuse cells with a deep-submicron thin/thick-gate-oxide process, and the identification of sensitive circuits using a pulsed laser are analyzed and discussed in Sect.3. For space applications, the aluminum shielding effect and space error rate are predicted and discussed in Sect. 4. 2 Experimental Setup 1 2.1 Devices under test (DUT) details 2 The 1-T anti-fuse PROM has a fast read speed and high storage density (8 Mbits and 16 Mbits). Its memory unit is shown in Fig. 1 Fig. 1 . A non-volatility memory cell is achieved with the thick and thin oxide anti-fuse technique. The cell was fabricated as a single transistor with a thin/thick oxide gate [ 10 10 ]. The thin oxide region (4.5 nm) is penetrated under the action of high voltage, leading to a conductive channel, while the thick part (7.5 nm) can withstand high voltage with its high resistance. The breakdown position is fixed on the edge of the thick and thin oxide film, which is called the Program Area. The DUTs were decapped before exposure in order to make swift heavy ions reach the sensitive regions. Each DUT adopted a 130-nm silicon epitaxial process with 16 layers including passivation and metal on top of the die. Compared with 8-Mbit PROMs, the storage of a single bit in a 16-Mbit PROM is achieved by two anti-fuse memory units in order to enhance its programming reliability. A guard ring structure can provide spatial and electrical isolation in CMOS circuits in order to prevent a Single Event Latch-Up (SEL). We fabricated p+ guard rings connected to the ground and enclosed the n+ sources in order to reduce the minority carriers in an NMOS. In a PMOS, n+ guard rings connected to high voltage were used to prevent the influence of minority carriers in the transistor. An EDAC verification code generated by a Hamming code and TMR in an internal latch employed a triple modular voter circuit. EDAC and TMR are two main SEU-hardened methods that will be further analyzed in Sect. 3. The DUTs were utilized in dynamic mode at room temperature, and the frequency was controlled at 20 MHz (cycle time: 50 ns) with a 1-A current limitation. The cycle time can affect the number of captured errors created by particle-induced transient pulses in peripheral CMOS circuits, and then can influence the effect of our error-correction methods (EDAC and redundancy). The DUT was employed using a serial addressing mode to read statistics, and its memories were continuously scanned by an FPGA-based tester. In the test process, the internal data in the DUT were a 00-FF circular sequence code. Once an error was detected, the error information including its address was recorded. Any error data and abnormal currents were investigated and presented on the screen. 2.2 Heavy-ion facility and parameters 2 Heavy-ion testing was carried out at the Heavy Ion Research Facility in Lanzhou (HIRFL) at the Institute of Modern Physics, Chinese Academy of Sciences, and at the HI-13 Tandem Accelerator at the China Institute of Atomic Energy. The flux of incident ions can be controlled at 10 4 ions·cm -2 ·s -1 . Most irradiation tests were performed in air with heavy ions passing through a vacuum/air transition foil. Both Al foils and air were used as energy degraders to adjust the beam energy. The swift heavy-ion parameters in the experiments are listed in Table 1 Table 1 [ 9 9 , 11 11 – 13 13 11–13 ]. Five kinds of heavy ions were used for DUT irradiation. Both the LETs and range values were calculated by using SRIM 2013 (in Table 1 Table 1 ). Although the HI-13 beams had inferior energy, the thicknesses of all upstream multilayers could still be penetrated. 1 1 Accelerator 1 1 Ion species 1 1 Initial energy (MeV) 1 1 LET (MeV·cm 2 ·mg -1 ) 1 1 Range in silicon (µm) 1 1 HI-13 1 1 28 Si 1 1 135.0 1 1 9.3 1 1 50.7 1 1 1 1 35 Cl 1 1 150.0 1 1 13.4 1 1 42.8 1 1 HIRFL 1 1 86 Kr 1 1 2150.0 1 1 19.6 1 1 343.2 1 1 1 1 209 Bi 1 1 1985.5 1 1 91.1 1 1 101.4 1 1 1 1 181 Ta 1 1 2262.5 1 1 80.5 1 1 99.3 2.3 Pulsed-laser testing system 2 A picosecond pulsed laser was employed to irradiate the DUT and gather the SEU signals in a timely manner. The test system ( Fig. 2 Fig. 2 ) was composed of an optical module, a high-energy pulse laser (with 1064-nm center wavelength and 25-ps pulse width), optical polarization, and an attenuation module. Laser pulse polarization and attenuation were achieved by combining filters that attenuated the beam to fixed amounts with polarizer/half-waveplate continuous variation. An energy monitoring and controlling system with operating software was used to control the energy changes from 1 nJ to 30 nJ. A camera was needed to image the surface of the DUT and focused laser spot, making it possible to identify which sensitive node was being tested by the pulsed laser [ 14 14 ]. Additionally, a three-dimensional mobile platform provided the DUT positional parameters directly in order to retain the accuracy and stability during the experiment. In the test, a topside irradiation mode with a 5-µm spot size was selected. Owing to the large feature size and low metal coverage rate in the DUT, incident photons from the top side easily reached the SEE sensitive nodes unhindered by metal interconnects or packaging [ 14 14 ]. Given the very small sizes of the sensitive nodes in the DUT, a stage with a step size of < 1 µm should be used. The pulsed-laser parameters illustrated above can effectively characterize the SEE both spatially and temporally. 3 Experimental Results and Analysis 1 This section presents the heavy-ion and pulsed-laser irradiation results. Owing to the thin/thick gate oxide anti-fuse process in the memory cell and the guard ring structures in the CMOS circuits, no SEL phenomena occurred in the DUT during the entire process. p + and n + guard rings were used to prevent the influence of minority carriers by keeping the wells within their appropriate potentials. It can be concluded that the DUTs possessed a strong capacity to resist SEL. Other testing results are presented as follows. First, the SEU cross sections with dynamic bit errors and address errors distinguished in the heavy-ion vertical incidence irradiation under different LET values were illustrated. Second, the effect of irradiation hardness techniques and the hard error influence were characterized and analyzed. Then, laser mapping results revealed the sensitive area, which was verified by additional 181 Ta irradiation. 3.1 Heavy-ion SEU test 2 DUTs with 8-Mbit and 16-Mbit configurations were irradiated by five swift heavy ions, and the SEU data were collected. SEUs in the DUTs mainly contained dynamic bit errors and address errors, as shown in Table 2 Table 2 . For the advanced thin/thick gate oxide anti-fuse process in the DUT memory block, each unit exhibited a high anti-irradiation performance. However, a few dynamic bit errors in the readout during irradiation were observed. This may have resulted from dynamic upsets in the output buffer, thus making a single bit error appear. The internal address counter in the DUT stores the information of the current address and any increments or resets. If a counter is upset, a subsequent reading will proceed from the new (upset) address [ 2 2 ]. The address encoded in the DUT identifies the current location. Apparently, most upsets in the counter may be owing to a single bit, but long-lasting multiple-bit upsets were also seen. 1 1 Error type 1 1 Error Address 1 1 NO Error 1 1 - 1 1 Dynamic Bit Error 07c0e3 1 1 prom: 67e6 sram: 6766 Dynamic Bit Error 1 1 NO Error 1 1 - 1 1 NO Error 1 1 - 1 1 NO Error 1 1 - 1 1 Address Error 002d08 1 1 prom: 0010 sram: 1110 Address Error 1 1 Address Error 002d09 1 1 prom: 0000 sram: 1312 Address Error 1 1 Address Error 002d0a 1 1 prom: 0000 sram: 1514 Address Error 1 1 Address Error 002d0b 1 1 prom: 0000 sram: 1716 Address Error 1 1 Address Error 002d0c 1 1 prom: 0100 sram: 1918 Address Error 2 1 ︙︙︙︙︙︙︙ Several Clock Cycles 1 1 NO Error 1 1 - Based on the recorded upset data, a Weibull function (as given below) was used to fit the heavy-ion-induced SEU data. <math display="block" id="M1"><mrow><mi>σ</mi><mo>=</mo><mrow><mo>{</mo><mrow><mo> </mo><mtable><mtr><mtd><mrow><msub><mi>σ</mi><mrow><mtext>sat</mtext></mrow></msub><mrow><mo>{</mo><mrow><mn>1</mn><mo>−</mo><mtext>exp</mtext><mrow><mo>[</mo><mrow><mo>−</mo><msup><mrow><mrow><mo>(</mo><mrow><mfrac><mrow><mi>L</mi><mi>E</mi><mi>T</mi><mo>−</mo><mi>L</mi><mi>E</mi><msub><mi>T</mi><mrow><mtext>th</mtext></mrow></msub></mrow><mi>w</mi></mfrac></mrow><mo>)</mo></mrow></mrow><mi>s</mi></msup></mrow><mo>]</mo></mrow></mrow><mo>}</mo></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mn>0</mn><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mi>L</mi><mi>E</mi><mi>T</mi><mo>≤</mo><mi>L</mi><mi>E</mi><msub><mi>T</mi><mrow><mtext>th</mtext></mrow></msub><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo></mrow></mtd></mtr></mtable></mrow></mrow><mi>L</mi><mi>E</mi><mi>T</mi><mo>≥</mo><mi>L</mi><mi>E</mi><msub><mi>T</mi><mrow><mtext>th</mtext></mrow></msub><mo>,</mo></mrow></math> where σ (cm 2 ·bit -1 ) is the SEU cross section in terms, σ sat (cm 2 ·bit -1 ) is the saturation upset cross section, LET th is the minimum LET to observe an error in the stored data, s is a dimensionless exponent, and w is a width parameter. The total gathered errors are shown in Fig. 3 Fig. 3 . For 8-Mbit PROMs, the LET threshold of the SEU is about 9.2 MeV·cm 2 ·mg -1 , with the saturation cross section at 1.0 × 10 -5 cm 2 ·device -1 . The 16-Mbit PROM has a similar LET threshold (9.6 MeV·cm 2 ·mg -1 ) but a higher-saturation cross section at 2.7 × 10 -5 cm 2 ·device -1 . The thresholds of two DUTs are almost identical, while the 16-Mbit PROM has a larger interaction area for charge deposition and collection, causing the probability for the interactions between heavy ions and the sensitive volumes in 16-Mbit PROM improved. This leads to a negligible increase in the SEU saturation cross section of the 16-Mbit PROM. However, when the saturated cross section values are normalized per bit, the two DUTs are roughly the same: 1.3 × 10 −12 cm 2 ·bit -1 (8 Mbit) and 1.7 × 10 −12 cm 2 ·bit -1 (16 Mbit). Upsets in address counters and I/O pairs result from a single bit, although a few multiple-bit upsets were observed. All of the address errors were measured and fitted by a Weibull function, as shown in Fig. 4 Fig. 4 . In the figure, the LET thresholds of the 8- and 16-Mbit PROMs are approximately 21.1 MeV·cm 2 ·mg -1 and 18.1 MeV·cm 2 ·mg -1 , respectively, with a saturation cross section at 9.7 × 10 −6 cm 2 ·device -1 (1.2 × 10 −12 cm 2 ·bit -1 ) and 1.3 × 10 −5 cm 2 ·device -1 (8.1 × 10 −13 cm 2 ·bit -1 ), respectively. The LET thresholds of the address data are higher than those of the stored data, but they play a primary role in the SEU rates with LET values between 22.4 and 37.6 MeV·cm 2 ·mg -1 . For several LET values, the rates of the address data can exceed 90%. A superior threshold may be derived from high reinforcement in the I/O ports and the TMR structure of the address counters. Above all, large I/O ports need to deposit more charge to trigger an upset, and a large critical charge is difficult to create in low-LET-irradiation conditions. On the other hand, all of the address counters with basic CMOS structures have TMR consolidation. An error signal pulse introduced by the external test environment must be loaded to significant parts such as the reset sites, and it eventually passes through the voter. These restrictive conditions increase the upset threshold. PROMs with 8-Mbit and 16-Mbit configurations adopt the same radiation hardening structure and obtain similar irradiation testing results. This shows that the sensitive circuits of these two devices are the same, and their anti-irradiation performance is mainly determined by reinforcement in the sensitive circuits. Thus, their overall anti-irradiation ability is better than that of several foreign products investigated in [ 1 1 , 2 2 ]. Here, EDAC and TMR, as two main reinforcement methods, decreased the saturation cross section of the error data in the 8-Mbit PROM and 16-Mbit PROM by approximately 10 -12 cm 2 ·bit -1 , indicating a good capacity to resist SEU. The EDAC verification code adopted by the DUTs is generated by a Hamming code with 32 plus 8 structures. In irradiation experiments, the EDAC function was used continuously. According to the data stored in the memory cells and the examined algorithms designed as EDAC codes, the testing system can determine whether errors appeared, and make corrections immediately. The TMR mode in the internal latch ( Fig. 5 Fig. 5 ) employs three logic cells to store the same data and select the correct output by a triple modular voter circuit. Error signals caused by heavy ions and captured by a latch or register need to satisfy three basic conditions: existence paths from the struck node to a latch or register, a proper arriving time, and a necessary profile at the latch input. Under TMR reinforcement in the latch circuits, even if an error signal is captured by the latches, there is still no guarantee that it will be transmitted to the output and pass the TMR voter. Compared to the statistics in the heavy-ion test in Ref. [ 2 2 ], the TMR structure in the latch circuit can reduce the upset rates to a great extent. However, the hardened effects of the TMR and EDAC techniques are affected by the cycle time. With the error accumulations in one period, dynamic bit errors may not be corrected by a one-error-correction Hamming code and are distinguished by a triple redundant voter in time, thereby providing the error information as the output. Additional large-fluence swift heavy-ion irradiation was used to check the program redundancy technique that existed in the 16-Mbit PROMs, which were created to enhance the reliability and decrease the influence of hard errors in memory cells. After high LET 209 Bi (91.1 MeV·cm 2 ·mg -1 ) irradiation for over a decade of cycles (each cycle was tested with nearly 10 8 ions), several hard errors appeared only in the 8-Mbit PROM (as shown in Table 3 Table 3 ), although the probability was extremely low and the rates were lower than 10 -6 . These persistent hard errors can be interpreted as irradiation damage created by swift heavy-ion irradiation in their program area, as shown in Fig. 6 Fig. 6 . 1 1 Error type 1 1 Error Address 1 1 Dynamic Bit Error: 0086b7 1 1 prom: ef6e sram: 6f6e 1 1 No error 1 1 - 1 1 Dynamic Bit Error: 0086b7 1 1 prom: ef6e sram: 6f6e 1 1 Dynamic Bit Error: 0086b7 1 1 prom: ef6e sram: 6f6e 1 1 No error 1 1 - Because of the thin and sensitive program areas in anti-fuse transistors, a large fluence of swift heavy ions can form surface roughness, ion tracks, irreparable damage, and can cause several unprogrammed cells to eventually become programmed. The experimental results revealed that an irreparable program can be created by high-LET 209 Bi particles, resulting in the occurrence and detection of 0-to-1 upset errors. However, taking both the space LET spectrum and the DUTs’ actual working states into consideration, this hard damage may not exist over a decade in geosynchronous orbit or medium earth orbit. This means that DUTs without programming-redundant design are still suitable for general space missions. However, for long-term space missions, this reliability-enhanced design seems to be a better choice. 3.2 Laser SEU test 2 Laser mapping images with sensitive areas marked by colored points are shown in Fig. 7 Fig. 7 . The scanning energy was continuously changed from 1 nJ to 30 nJ, and the experimental manipulation was repeated to radiate the DUT in the full-exposure area [ 15 15 , 16 16 ]. The energy values in Fig. 7(a), (b), and (c) Fig. 7(a), (b), and (c) indicate the laser thresholds of the power source, I/O pairs, and internal circuits, respectively, by comparing them with the schematic view of the DUT in Fig. 7(d) Fig. 7(d) . Each mapping image is repeated at least three times. The internal power source module in the upper right corner of Fig. 7(d) Fig. 7(d) is the most sensitive part because the circuit around the power source is extremely difficult to reinforce. The experimental results proved the significance of this issue. In addition, the I/O pairs connected to the data output in the peripheral circuits showed errors when the laser energy was 13 nJ or higher. This corresponded to the higher threshold in the large reinforced I/O pairs of the heavy-ion test. Then, a few error data items near the center of the DUT occurred; these increased in areas and at rates where the laser energy increased. Errors that occurred in the middle area of the DUT are reading comparison circuits. These dynamic circuits are used to store and compare the data in continuous modes. When ions or a laser strikes, the transient pulses eventually appear and propagate in the comparison circuit. When laser energy increases, the data in the latch circuits has a few errors. Nevertheless, the increased error rates and sensitive areas in the reinforcement latch circuits can be neglected. The laser experiment verified the excellent radiation resistance of the DUT for the areas of stored data that were not very sensitive to photons, or where upsets may be detected and corrected by the EDAC code TMR voter in time. The address bits have a high SEU threshold, but when the laser energy is higher (>8.5 nJ), error data cannot be corrected by the voter and EDAC in time owing to the surging of long-lasting and successive upsets. The power source, I/O pairs, and peripheral circuit without hardness designs are SEU-sensitive areas revealed by laser irradiation. Using only a large-size hardness technique in the I/O pairs cannot totally prevent SEUs. Nevertheless, I/O blocks in the PROM will not be operated until the FPGA demands to be configured in an actual space environment. This takes effect under the intermittent operation working condition only when the stored information required to be transmitted rather than under the continuous working mode in the entire SEE ground test, thus sharply declining the SEU risk. In addition, without further reinforcement in the I/O pairs, the saturated cross section of this PROM was fairly small already, which revealed its excellent antiradiation performance to satisfy space requirements. Accelerated 181 Ta ions with an energy of 12.5 MeV·u -1 were used to reexamine the pulsed laser testing results by adding 2-mm Al foils above the internal power source on the right part of the DUT and all I/O pairs. The calculated saturation cross section was 4.1 × 10 −6 cm 2 ·device -1 , which declined significantly when compared with its initial value (2.7 × 10 −5 cm 2 ·device -1 ). This verified that in the pulsed laser test, the I/O pairs and internal power source contributed the majority of the upset rates. 4 Prediction of error rate in space applications 1 SEUs induced by heavy ions in space were calculated by CRÈME-96 and CRÈME-MC based on the RPP model extracted by the DUT structure [ 17 17 – 19 19 17–19 ]. Geosynchronous orbit, as one of the most serious environments to be influenced by heavy ions, was chosen to evaluate the upset rates of the DUT behind different Al-shielding thicknesses. 4.1 RPP model extraction 2 Simulation tools based on the Monte Carlo method were used. The effective calculation area was divided equally per bit and can be calculated by the following formula: <math display="block" id="M2"><mrow><msub><mi>S</mi><mrow><mtext>bit</mtext></mrow></msub><mo>=</mo><mo> </mo><mo> </mo><mfrac><mrow><msub><mi>S</mi><mrow><mtext>total</mtext></mrow></msub></mrow><mi>N</mi></mfrac><mo>,</mo><mo> </mo><mo> </mo><mo> </mo><mo> </mo></mrow></math> where N is the total number of bits in the PROM. S total is the actual area of the DUT, and S bit is an equivalent single-bit area. Then, the sensitive area per bit per square centimeter ( σ bit ) can be calculated based on the experimental results summarized above. For a 16-Mbit PROM, σ bit is 1.7 × 10 -12 cm 2 . Experimental heavy ions were used to irradiate the model of the PROM. Beams were set at normal incidence with a zenith angle of 0º to directly radiate the DUT model built in Fig. 8 Fig. 8 . The particle fluence was controlled at 4.0 × 10 10 ions·cm -2 . Based on the device parameters and Eq. (2), the depth of the sensitive volume was set at 1 μm. The relation between the energy deposition in the entire sensitive volume and the cross section in space can be calculated by using the Crème-MC simulator [ 17 17 – 19 19 17–19 ]. The collected charge ( Q c ) can be determined based on the results of the RPP selection and their ascertained energy deposition. For Si devices, Q c associated with an individual particle event can be calculated by a linear combination of the energy deposited in each volume ( E i ). This can be written as [ 17 17 ] <math display="block" id="M3"><mrow><msub><mi>Q</mi><mtext>c</mtext></msub><mo>=</mo><mfrac><mrow><mn>1</mn><mo> </mo><mtext>pC</mtext></mrow><mrow><mn>22.5</mn><mo> </mo><mtext>MeV</mtext></mrow></mfrac><munder><mstyle mathsize="140%" displaystyle="true"><mo>∑</mo></mstyle><mi>i</mi></munder><msub><mi>α</mi><mi>i</mi></msub><msub><mi>E</mi><mi>i</mi></msub><mo>.</mo></mrow></math> The depth ( H sv ) of the volume is related to the critical charge ( Q cri ). Since the energy to produce an electron hole pair in silicon is a constant equivalent to 3.6 eV, Q cri can be defined by [ 17 17 ] <math display="block" id="M4"><mrow><msub><mi>Q</mi><mrow><mtext>cri</mtext></mrow></msub><mo>=</mo><mn>10.35</mn><mo>×</mo><mi>L</mi><mi>E</mi><msub><mi>T</mi><mrow><mtext>th</mtext></mrow></msub><mo>×</mo><msub><mi>H</mi><mrow><mtext>sv</mtext></mrow></msub><mo>,</mo></mrow></math> where LET th in Eq. (4) indicates the LET threshold values, and H sv is in micrometers. By combining Eq. (3) and Eq. (4), E i can be determined [ 17 17 ]. It is obvious that the cross section of 28 Si and 35 Cl is slightly below 10 -13 cm 2 ·bit -1 , which is close to the LET threshold in the heavy-ion test (around 10 -13 cm 2 ·bit -1 ). In addition, the cross section obtained by the simulation of 209 Bi is approximately 1.9 × 10 -12 cm 2 ·bit -1 , which matches the experimental saturation cross section at 1.7 × 10 -12 cm 2 ·bit -1 . Thus, the established RPP model for space prediction fits well with the experimental results. 4.2 Calculation of error rates 2 The prediction of heavy-ion SEU rates (R) in space is accomplished based on the measured cross sections in the heavy-ion test and the ion flux in a given orbit obtained by Crème-96 [ 20 20 , 21 21 ]. It is calculated by <math display="block" id="M5"><mrow><mi>R</mi><mo>=</mo><msub><mrow><munderover><mstyle mathsize="140%" displaystyle="true"><mo>∫</mo></mstyle><mn>0</mn><mi>∞</mi></munderover></mrow><mrow><mtext>eff</mtext></mrow></msub><mrow><mo>(</mo><mrow><mi>L</mi><mi>E</mi><mi>T</mi></mrow><mo>)</mo></mrow><mtext>σ</mtext><mrow><mo>(</mo><mrow><mi>L</mi><mi>E</mi><mi>T</mi></mrow><mo>)</mo></mrow><mtext>d</mtext><mi>L</mi><mi>E</mi><mi>T</mi><mo>,</mo></mrow></math> σ ( LET ) is the effective cross section, i.e., it can be averaged on all solid angles (as shown in Fig. 8 Fig. 8 ). The sensitive volume was irradiated by heavy ions in space from 4π solid angles. Here, Φ eff is a differential ion-flux spectrum for a given shielding thickness in geosynchronous orbit in a solar maximum condition [ 20 20 ]. Fig. 9 Fig. 9 proves that with a shielding thickness over 3 mm, Al may provide promising results in reducing SEU rates. Based on the constructed RPP model in Creme-MC and the calculated Q cri , the SEU rates caused by heavy ions in space were calculated and are shown in Fig. 10 Fig. 10 . Shielding by 10-mm Al produced a superior protection effect with a low event rate of 6.26 × 10 -13 upset·bit -1 ·day -1 . The calculated event rate is matched to continuous working conditions such as a ground test. This may be a few orders larger than its actual intermittent operation mode in space. 5 Discussion 1 Our experimental results in heavy-ion and pulsed laser tests revealed the radiation-hardened performance of 8-Mbit and 16-Mbit PROMs. DUTs fabricated by the thin/thick gate oxide anti-fuse process with additional EDAC- and TMR-hardened design have excellent application prospects, significantly decreasing the SEU risk. In peripheral logic circuits, swift heavy ions incident to a particular sensitive node with charge deposition may generate a transient pulse. Then, the transient pulse may create upset errors, but this is mainly determined by the particles’ striking positions and the arrival time of the transient pulse in circuits. The striking positions of the particles affect the pulse width and amplitude in CMOS circuits. In addition, the arrival time of a transient pulse is essential because the pulse signal may be captured by a latch or register circuits only within the rising edge of the clock. [ 21 21 , 22 22 ]. Otherwise, a transient pulse may be blocked during the following clock period and eliminated by a scribing operation, or removed by special hardness techniques [ 22 22 , 23 23 ]. Moreover, taking the TMR structure into consideration, even if an upset error exists in one latch, it still cannot influence the output voter results. Additional 209 Bi (1985.5 MeV) and 181 Ta (2262.5 MeV) were chosen to check the programming reliability and the effectiveness of the laser test, respectively. Further, high-fluence 209 Bi irradiation verified the formation and proportion of the hard errors. Irradiation damage created by swift heavy ions with high LET values can destroy anti-fuse memory units, cause irreparable damage , and finally program the unprogrammed cells. However, the 16-Mbit PROM completely eliminated hard errors by storing a single bit in two anti-fuse memory units. This enhanced the reliability of the DUT to a great extent, especially for long-term orbiting satellites. The saturation cross section declined significantly in 181 Ta irradiation when the internal power source and I/O pairs were maintained under the protection of aluminum foils. The results of 181 Ta irradiation matched well with the laser test, which indicated that superior anti-irradiation performance can be achieved by hardening the power source and I/O pairs, although the upset rate for the DUT in space is extremely low. 6 Conclusion 1 The 130-nm CMOS-based thin/thick gate oxide anti-fuse PROM reinforced by EDAC and TMR techniques had an extremely low saturation cross section in heavy-ion radiation tests. Dynamic bit errors mainly caused by the dynamic upsets in the output buffer have a low LET threshold for the CMOS process, while address errors have high thresholds but long-lasting influence. The 16-Mbit PROM passed a programming reliability test with zero hard errors appearing during the high-fluence 209 Bi irradiation. A laser test revealed that in the vicinity of the internal power source module and I/O ports are sensitive areas, although the large-size techniques in the I/O blocks improved their SEU thresholds. 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Sci . 42 , 2127 - 2137 ( 1995 ). doi: 10.1109/23.489263 http://doi.org/10.1109/23.489263 Temporal analysis of SEU in SOI/GAA SRAMs 10.1007/s41365-019-0602-6 This work was supported by the National Natural Science Foundation of China (Nos. 11690041, 11805244, and 11675233) and the Opening Project of Science and Technology on Reliability Physics and Application Technology of the Electronic Component Laboratory (No. ZHD 201604). 2018-08-08 2018-10-10 2018-10-20 2019-04-13 2019-05-01 2021-04-10 © China Science Publishing & Media Ltd. (Science Press), Shanghai Institute of Applied Physics, the Chinese Academy of Sciences, ChineseNuclear Society and Springer Nature Singapore Pte Ltd. 2019 This is a post-peer-review, pre-copyedit version of an article published in Nuclear Science and Techniques. The final authenticated version is available online at: http://dx.doi.org/10.1007/s41365-019-0602-6 http://dx.doi.org/10.1007/s41365-019-0602-6 . 2019 Nuclear Science and Techniques 05 30