Carry-chain propagation delay impacts on resolution of FPGA-based TDC
NUCLEAR ELECTRONICS AND INSTRUMENTATION|Updated:2021-01-20
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Carry-chain propagation delay impacts on resolution of FPGA-based TDC
Nuclear Science and TechniquesVol. 25, Issue 3, Article number: 030401(2014)
Affiliations:
1.State Key Laboratory of Particle Detection & Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei230026, China
2.Anhui Key Laboratory of Physical Electronics, Hefei230026, China
The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy.
Zhou J, Liu S, Yin C, et al. Nucl Sci Tech, 2011, 22: 372-377.
Eugen B and Michael T. IEEE T Nucl Sci, 2011, 58: 1547-1552.
Altera Corporation. Documentation: Cyclone II Device Handbook, Chapter 2. Cyclone II Architecture. http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdfhttp://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf (Feb 2007).
Altera Corporation. Documentation: Stratix IV Device Handbook. http://www.altera.com.cn/literature/hb/stratix-iv/stratix4_handbook.pdfhttp://www.altera.com.cn/literature/hb/stratix-iv/stratix4_handbook.pdf (Sep 2012)
Xilinx Corporation. Virtex-4 FPGA User Guide. http://www.xilinx.com/support/documentation/user_guides/ug070.pdfhttp://www.xilinx.com/support/documentation/user_guides/ug070.pdf (Dec 2008).
John P U, Introduction to VLSI circuits and systems, Hoboken, J. Wiley, 2002: 250-294.
Wu J, Shi Z, Wang I Y. NSSMIC.2003.1352025: Firmware-only implementation of time-to-digital converter (TDC) in field programmable gate array (FPGA), in Proc. IEEE Nuclear Science Symposium.Portland, OR, USA, Oct. 2003, 177-181.
Pelka R, Kalisz J, Szplet R. IEEE T Instrum Meas, 1997, 46: 449-453.
Wu J, Shi Z. The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay, in Proc.IEEE Nuclear Science Symposium, Dresden, Germany, Oct 2008, 3440-3446.
Wang J, Liu S, Qi S, et al. IEEE T Nucl Sci, 2009, 57: 446-450.
Song J, An Q, Liu S. IEEE T Nucl Sci, 2006, 53: 236-241.