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A low dead time vernier delay line TDC implemented in an actel flash-based FPGA

NUCLEAR ELECTRONICS AND INSTRUMENTATION | Updated：2021-01-20

- A low dead time vernier delay line TDC implemented in an actel flash-based FPGA Cover Article Enhanced Publication
- Nuclear Science and Techniques Vol.24, Issue 4, (2013)
- Affiliations：
  
  State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China,Hefei,China,230026;Department of Modern Physics, University of Science and Technology of China,Hefei,China,230026
- Author bio：
- Funds：
- DOI：10.13538/j.1001-8042/nst.2013.04.012 CLC：
- Published：01 August 2013，
  
  Published Online：，
  
  Received：20 January 2013，
  
  Revised：，
  
  Accepted：
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Cite this article
Xi QIN, Changqing FENG, Deliang ZHANG, et al. A low dead time vernier delay line TDC implemented in an actel flash-based FPGA. [J]. Nuclear Science and Techniques 24(4):040403(2013)
DOI：

Xi QIN, Changqing FENG, Deliang ZHANG, et al. A low dead time vernier delay line TDC implemented in an actel flash-based FPGA. [J]. Nuclear Science and Techniques 24(4):040403(2013) DOI： 10.13538/j.1001-8042/nst.2013.04.012.

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A low dead time vernier delay line TDC implemented in an actel flash-based FPGA Cover Article Enhanced Publication