Offset-free DC-coupled analog frontend circuit for high-dynamic-range signals

Offset-free DC-coupled analog frontend circuit for high-dynamic-range signals 1 2 corresp first-author Corresponding author, dyf13@tsinghua.org.cn Corresponding author, dyf13@tsinghua.org.cn dyf13@tsinghua.org.cn https://orcid.org/0000-0002-7833-1729 2 2 2 1 Department of Engineering Physics, Tsinghua University, Beijing 100084, China Department of Engineering Physics, Tsinghua University, Beijing 100084, China Institute of Nuclear Physics and Chemistry, China Academy of Engineering Physics, Mianyang 621900, China Institute of Nuclear Physics and Chemistry, China Academy of Engineering Physics, Mianyang 621900, China The analog frontend (AFE) coupling circuit is a crucial processing element for data acquisition systems based on analog-to-digital converters (ADCs). Currently, high-speed and high-resolution ADCs are predominantly designed with differential input stages. Conventional high-speed ADC drivers are mainly AC-coupled by employing transformers (Baluns) or fully differential amplifiers (FDAs) with blocking capacitors. However, the results of this study indicate that a certain degree of DC offset error exists and manifests itself as the baseline error in the presence of power dividers connecting several DC-coupled channels that implement high-dynamic-range (HDR) signal conditioning. The study involves a theoretical analysis and explanation of the baseline offset error. The offset error can potentially lead to unexpected out-of-range issues for sampling devices, including high-speed ADCs and switched capacitor array ASICs. High-performance FDAs are adopted, and an offset-free DC-coupled AFE circuit is proposed to address the aforementioned issue using two-stage amplification and a resistive attenuator. The proposed methodology is verified via circuit simulations and hardware design. Thus, the baseline offset problem can be accurately solved using the proposed circuit by minimizing the neglectable error. The proposed circuit facilitates improvements in the high-precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC-coupling scheme with FDAs involving resistive power dividers. Offset-free DC-coupled Two-stage amplification Resistive attenuator High-Dynamic-Range 1 Introduction 1 Recently, high-speed digitizers or data acquisition systems have been widely used to record individual signals in nuclear and particle physics experiments. The analog frontend (AFE) circuit is a crucial processing element for data acquisition systems and is based on either high-speed analog-to-digital converters (ADCs) or switched capacitor arrays (SCA). High-speed and high-resolution sampling devices (ADCs and SCAs) are predominantly designed with differential input stages owing to their excellent noise rejection [ 1 1 ]. Conventional coupling circuits are mainly AC-coupled, employing transformers (Baluns) [ 2 2 - 4 4 2-4 ] or fully differential amplifiers (FDAs) with blocking capacitors [ 5 5 - 7 7 5-7 ]. Previous studies in the field of AFE design for high-speed data acquisition mainly focused on AC-coupling [ 2 2 , 4 4 - 6 6 4-6 , 8 8 - 12 12 8-12 ], whereas some designs used the DC-coupled circuit with FDAs to achieve wide-band AFE [ 13 13 , 14 14 ]. However, there is a paucity of studies on the potential baseline error that results from the non-zero common-mode voltage in the presence of resistive power dividers connecting adjacen t channels. In the high-precision measurement of high-dynamic-range (HDR) signals in some nuclear and particle physics experiments, conventional AFE adopts different sets of power dividers and attenuators to cover a wide dynamic range [ 15 15 , 16 16 ]. Therefore, the offset issue can negatively affect measurement accuracy in the connection scheme. Therefore, this study highlights the offset issue that results from the resistive power divider connecting several DC-coupled channels via FDAs. Additionally, this study proposes a new methodology to address the offset issue using the processing circuit. 2 Background theory 1 The "split-range scheme" referred in the study corresponds to a conventional technique to receive HDR signals. For example, in the two-split scheme, the HDR signal is initially split to two parallel paths by a power divider and then attenuated to different ranges by individual attenuating factors A 1 and A 2 , as shown in Fig. 1 Fig. 1 . Operational amplifiers correspond to typical ADC drivers to implement essential signal conditioning. a. Resistive Power dividers The aim of the study is to achieve DC-coupled AFE, and thus resistive devices are satisfactory. To split the wide range of the input signal, a resistive power divider that serves as a splitter in Fig.1 Fig.1 is employed to replicate signals. In the design, the reflection coefficients correspond to critical parameters to characterize the isolation of the resistive power dividers. b.Resistive attenuators In the split-range scheme, a simple " π " attenuator, as shown in Fig. 2 Fig. 2 , can function in different input-range selections using appropriate resistors. The corresponding values of R A and R B are calculated based on Eq.(1), where A denotes the attenuating factor. <math display="block" id="M1"><mrow><msub><mi>R</mi><mtext>A</mtext></msub><mo>=</mo><mi>Z</mi><mo>⋅</mo><mfrac><mrow><msup><mi>A</mi><mn>2</mn></msup><mo>−</mo><mn>1</mn></mrow><mrow><mn>2</mn><mi>A</mi></mrow></mfrac><mtext> </mtext><mtext> </mtext><msub><mi>R</mi><mtext>B</mtext></msub><mo>=</mo><mi>Z</mi><mo>⋅</mo><mfrac><mrow><mi>A</mi><mo>+</mo><mn>1</mn></mrow><mrow><mi>A</mi><mo>−</mo><mn>1</mn></mrow></mfrac></mrow></math> c. Single-ended-to-differential (SE-DE) conversion Most real-world signals are single-ended, and a typical schematic is presented to illustrate SE-DE conversion based on an FDA in Fig. 3 Fig. 3 [ 17 17 ]. To ensure balanced feedback factors and impedance matching, the accurate value of each corresponding resistor is calculated based on [ 18 18 ]. The study emphasizes the non-zero common-mode voltage V OCM in differential signal design and processing via an FDA. 3 Model and Analysis 1 Based on the background theory described above, this section analyzes the generation of the baseline error in the split-range scheme via DC-coupled one-stage amplification using an FDA. Figure 4 Figure 4 provides an overview of the connection scheme of the signal generator, power divider, and two signal acquisition channels (CHA and CHB). All the discrete components in the signal path are resistive to satisfy the DC-coupling requirement. a. DC Offset voltage resulting from V OCM When there is zero input, the differential output voltage V ON and V OP , as shown in Fig. 4 Fig. 4 , correspond to V OCM . After imposing the input signal, the resulting output signal is equivalently treated as a differential-mode component superimposed by V OCM . In principle, the DC component V OCM at the differential output terminals is always fed back to the input ports (A node and B node denoted in Fig. 4 Fig. 4 ) based on voltage division rule, and thus the offset voltage V off is expressed in Eq. (2). <math display="block" id="M2"><mrow><msub><mi>V</mi><mrow><mtext>off</mtext></mrow></msub><mo>=</mo><mfrac><mrow><msub><mi>R</mi><mrow><mtext>TS</mtext></mrow></msub></mrow><mrow><msub><mi>R</mi><mrow><mtext>TS</mtext></mrow></msub><mo>+</mo><msub><mi>R</mi><mtext>G</mtext></msub><mo>+</mo><msub><mi>R</mi><mtext>F</mtext></msub></mrow></mfrac><msub><mi>V</mi><mrow><mtext>OCM</mtext></mrow></msub></mrow></math> The study emphasizes the self-consistency of the circuit in Fig.3 Fig.3 and does not lead to any additional error resulting from V OCM in the normal case. b.Baseline error generation due to resistive power divider The power divider in Fig.4 Fig.4 corresponds to a one-to-two splitter and the reflection coefficient S ij = 1/2. Hence, we can express the level of the baseline error Δ V off as in (3). <math display="block" id="M3"><mrow><mi>Δ</mi><msub><mi>V</mi><mrow><mtext>off</mtext></mrow></msub><mo>=</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><msub><mi>V</mi><mrow><mtext>off</mtext></mrow></msub><mo>=</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mfrac><mrow><msub><mi>R</mi><mrow><mtext>TS</mtext></mrow></msub></mrow><mrow><msub><mi>R</mi><mrow><mtext>TS</mtext></mrow></msub><mo>+</mo><msub><mi>R</mi><mtext>G</mtext></msub><mo>+</mo><msub><mi>R</mi><mtext>F</mtext></msub></mrow></mfrac><msub><mi>V</mi><mrow><mtext>OCM</mtext></mrow></msub></mrow></math> To provide a quick description of the magnitude of the baseline error, the study considered the typical FDA LMH5401 from Texas Instruments as an example to illustrate the degree of error level at the input terminal based on Eq. (3) via calculating the corresponding parameters in the Tab.2 from [ 19 19 ]. We selected a parameter η = Δ V off / V OCM to represent the level of the offset error as shown in Table 1 Table 1 . The table shows the value of η to be as high as 10%. This indicates that for a typical 1.25-V common-mode voltage, the value of Δ V off at the input terminal can correspond to 125 mV. As shown in Table 1 Table 1 , the generated baseline error should not be ignored in high-precision measurements. 1 1 A V (V/V) 1 1 R G (Ω) 1 1 R F (Ω) 1 1 R TS (Ω) 1 1 η (%) 1 1 2 1 1 90.9 1 1 200 1 1 30.1 1 1 4.7 1 1 4 1 1 22.6 1 1 152 1 1 43.9 1 1 10.0 1 1 8 1 1 12.1 1 1 250 1 1 48.3 1 1 7.8 1 1 10 1 1 9.76 1 1 300 1 1 47.8 1 1 6.7 1 1   c.Discussion Figure 4 Figure 4 presents the case when the external signal is connected to the positive input terminal. The offset voltage does not change even if the signal is connected to the negative input terminal given that V OCM is common to the two differential output terminals. Therefore, the two connection schemes lead to the same voltage although the reverse polarity offset error is observed at the output port in the presence of a resistive power divider. Despite the self-consistency of the circuit, a certain constant output voltage manifests itself as an undesirable baseline error in the split-range scheme. Unfortunately, the offset error potentially leads to an unexpected out-of-range issue for sampling devices including high-speed ADCs and SCA ASICs. This can constitute a significant issue for any applications with DC-coupled FDAs serving as the input driver and involving resistive power dividers. Traditionally, offset error is assessed within the scope of one single channel due to the intrinsic character of amplifier devices. However, there is paucity of studies on the offset error due to the resistive power divider in the split-range scheme. 4 Methodology and Verifications 1 4.1 Proposed methodology 2 The analysis in the previous section indicated that the baseline error was primarily caused by the non-zero V OCM in the split-range scheme. A direct method to address the issue involves blocking the DC voltage with a series of capacitors although the technique is not satisfactory for the DC-coupling requirement. Given the background, the current study proposed a processing circuit based on two-stage amplification and resistive attenuator to minimize the offset voltage V off (and the baseline error Δ V off ) such that it is neglectable. This corresponds to the meaning of the term "offset-free" in the study. At the first amplification stage, the common-mode voltage V OCM is set to zero, i.e., connected to the ground. The zero V OCM value does cause offset voltage in principle, and SE-DE conversion is implemented at this stage. The second stage shifts differential signals to the optimal input range of the ADC or SCA ASIC. Hence, at this stage, the V OCM should be normally set to non-zero. The DC path connecting the input terminal remains unblocked, and this still creates a minimized version of the offset voltage. Nevertheless, the resistive attenuator presented in Fig. 1 Fig. 1 with a suitable A further attenuates the offset voltage such that it is neglectable; and the following section demonstrates this point. 4.2 Verification by Simulations 2 To verify the proposed methodology, four types of simulation circuits with different structure characters were constructed in the NI Multisim environment. The structure characters and simulation objectives of the four types of circuits (referred to (a-1), (a-2) and (b-1), (b-2) circuits) are listed in Table 2 Table 2 . Specifically, the(a-1) circuit was used to identify the baseline offset error in the split-range scheme while (b-2) circuit was created to verify the proposed circuit. Additionally, (a-2) and (b-1) circuits were constructed to demonstrate the single effect of an additional amplification stage and attenuator, respectively. For the purpose of simplicity, the attenuating factors A 1 and A 2 , as shown in Fig.1 Fig.1 , were both set to 4. 1 1 Type code 1 1 Structure characters 1 1 Objectives 1 1 (a-1) 1 1 one stage, without attenuator 1 1 Identifying the baseline offset error 1 1 (a-2) 1 1 one stage, with attenuator 1 1 Verifying the function of attenuator 1 1 (b-1) 1 1 two stages, without attenuator 1 1 Verifying the function of two-stage amplification 1 1 (b-2) 1 1 two stages, with attenuator 1 1 Verifying the proposed circuit The simulations highlight the comparison of results from the virtual oscilloscope XSC1 in Fig.3 Fig.3 between one independent separated signal channel and another channel in the split-range scheme via a resistive power divider. For the purposes of brevity, the former is hereafter termed as single scheme while the latter is termed as split scheme. The simulation schematic for (b-2) circuit (the proposed circuit in the study) in single and split schemes is shown in Fig. 5, and (a-1), (a-2), and (b-1) Fig. 5, and (a-1), (a-2), and (b-1) simulation schematics are determined by modifying this circuit. a.Zero-input condition First, a zero input was applied to identify the baseline offset error and compare the levels of the error among the four types of circuits. The simulation results are shown in Fig. 6A Fig. 6A . In each of the four sub-figures, the blue and red plots denote the results of the single and split schemes, respectively. The difference between the red plot and blue plot in the first three sub-figures indicates that output signals were superimposed by offset errors in the split scheme. However, a clear trend of decreases in the offset error level was observed from (a-1) to (b-2) circuit. The baseline error of the proposed (b-2) circuit was minimized as significantly small. In the zero-input condition, the output signal actually corresponded to the baseline, and the baseline should theoretically be at the zero level. To quantitively describe the decreasing trend for the four type circuits, the baseline errors are summarized and presented in the second column of Table 3 Table 3 . The results confirmed that the baseline error was minimized from 486.7 mV to a sufficiently low value of 0.6 mV. Additionally, the baseline value from (a-1) to (a-2) was observed as minimized to 1/16, thereby verifying the significant effects of the resistive attenuator. 1 1 Case 1 1 Baseline error1 (mV) 1 1 Baseline error2 (mV) 1 1 (a-1) 1 1 486.7 1 1 486.8 1 1 (a-2) 1 1 30.9 1 1 31.0 1 1 (b-1) 1 1 14.0 1 1 14.0 1 1 (b-2) 1 1 0.6 1 1 0.6 b.Non-zero-input condition Second, a sinusoidal signal was applied to conduct simulations on non-zero-input condition. The amplitude of the sinusoidal signal in the respective circuit was configured to achieve a theoretical peak-to-peak value corresponding to 200 mV for the differential signal observed at the output ports. The simulation results are organized and shown in Fig. 6B Fig. 6B . Evidently, the baseline errors in the four type circuits were significantly reduced. On the non-zero-input condition, the baseline errors calculated from the simulation results are statistically summarized in the third column of Table 3 Table 3 . Furthermore, a comparison of the "Baseline error1" with "Baseline error2" in Table 3 Table 3 revealed that the baseline error exhibited a fixed pattern based on circuit parameters including relevant resistors and connecting schemes. 4.3 Verification by hardware design 2 Based on the proposed (b-2) circuit, this study designed a PXI 3U board in the Cadence environment. The hardware-design block diagram of the proposed AFE circuit is shown in Fig.7 Fig.7 . With respect to the FDAs, LMH5401 devices were employed as the ADC driver to implement two-stage amplification and signal conditioning. A photograph of the PXI 3U board with four channels is presented in Fig.8 Fig.8 (The baseline shift, trigger generation and distribution, and PXI configuration modules were also designed on the board. However, the parts are not within the scope of the study). The most direct way to implement the test of the board was to measure at the input terminal in no-input state given that the baseline errors were caused by the non-zero DC offset voltage at the input terminal in the split-range scheme. After putting the board in a slot of the PXI 1042 chassis, we used a multimeter (Fluke 87V) to measure terminal voltage and obtained a zero value. Additionally, a LeCroy oscilloscope (HDO6054) was also used to measure the DC voltage and observe the effective baseline submerged in the background noise. The results indicated the absence of detectable offset voltage observed at the input ports using either a Fluke 87V multimeter or a LeCroy oscilloscope, which consequently led to the absence of significant baseline errors in the presence of a resistive power divider in the split-range scheme. 5 Discussion and Conclusion 1 5.1 Discussion 2 The current methodology was proposed from the hardware-design perspective. Theoretically, the non-block DC path indicated that the baseline error cannot be completely eliminated by the proposed AFE circuit. To clearly disclose the essential cause of the baseline error, the simulation circuits herein did not consider non-idealities that can affect specific values of the results. Although the simulation setup appeared to be highly ideal and the hardware verification did not appear to be adequately accurate, improvements in the proposed circuit were evident. In a certain sense, the problem was actually solved from the engineering application perspective via minimization of the error to the point of it being negligible. Additionally, the offline correction procedure can also be applied to solve the problem after essential calibrations are performed because the baseline error exhibits a fixed pattern for a given circuit structure in a specific connection scheme. The significant merit of offline correction corresponded to the absence of increased complexity in hardware design although it suffered from the drawback of requiring tedious work. Furthermore, the calibration is not self-adaptable and should be conducted again in the case of changes for the circuit characters. Additionally, the baseline offset error correction can also be implemented online with a potentiometer that is connected to the un-driven side. As shown in the TIDA-00826 design guide, with respect to the DC-coupled input, the potentiometer is employed to apply an appropriate DC correction, nulling the possible DC offset and matching the DC voltage of the input signal [ 20 20 ]. A comparison of the two correction schemes indicated that the proposed methodology constituted a more direct solution albeit the increased complexity in hardware design. However, it is beyond the scope of this study to examine a specific solution to the DC offset problem for high-performance oscilloscopes. 5.2 Conclusion 2 This study indicates that the conventional self-consistent ADC driver using a DC-coupled FDA can cause an additional baseline error and consequently lead to unexpected out-of-range issues for sampling devices. The offset error is a major concern for HDR signals or any applications in the DC-coupling scheme involving resistive power dividers. After exploring the mechanism of the baseline error using the model and analysis, an offset-free DC-coupled AFE circuit based on two-stage amplification and a resistive attenuator was proposed to minimize the unwanted voltage. Essential simulations were implemented in an NI Multisim environment, and the proposed methodology was verified. Furthermore, a PXI 3U board was designed to verify the effects of the proposed circuit. Although this study successfully addressed the baseline error from an engineering perspective, it presents a limitation in that an appropriate attenuating factor " A " should be guaranteed. Despite its limitations, the study is certainly expected to significantly contribute to the high-precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC-coupling scheme with FDAs involving resistive power dividers. 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(Science Press), Shanghai Institute of Applied Physics, the Chinese Academy of Sciences, ChineseNuclear Society and Springer Nature Singapore Pte Ltd. 2020 This is a post-peer-review, pre-copyedit version of an article published in Nuclear Science and Techniques. The final authenticated version is available online at: http://dx.doi.org/10.1007/s41365-020-0746-4 http://dx.doi.org/10.1007/s41365-020-0746-4 . 2020 Nuclear Science and Techniques 4 31