Signal modeling and impulse response shaping for semiconductor detectors

Signal modeling and impulse response shaping for semiconductor detectors 1 2 first-author 1 corresp * zjb@cdut.edu.cn (Jian-Bin Zhou). * zjb@cdut.edu.cn (Jian-Bin Zhou). zjb@cdut.edu.cn https://orcid.org/0000-0003-4043-6733 1 https://orcid.org/0000-0003-3765-6030 1 2 https://orcid.org/0000-0003-1153-4350 1 https://orcid.org/0000-0002-0566-2308 1 3 https://orcid.org/0000-0003-3177-7069 College of Nuclear Technology and Automation Engineering, Chengdu University of Technology, No. 1 East 3 Road, Erxian Bridge, Chenghua District, Chengdu 610059, China College of Nuclear Technology and Automation Engineering, Chengdu University of Technology, No. 1 East 3 Road, Erxian Bridge, Chenghua District, Chengdu 610059, China Jiangxi Engineering Technology Research Center of Nuclear Geoscience Data Science and System, East China University of Technology, Nanchang 330013, China Jiangxi Engineering Technology Research Center of Nuclear Geoscience Data Science and System, East China University of Technology, Nanchang 330013, China China Testing Technology Co., Ltd., Chengdu 610021, China China Testing Technology Co., Ltd., Chengdu 610021, China The output-signal models and impulse response shaping (IRS) functions of semiconductor detectors are important for establishing high-precision measurement systems. In this paper, an output-signal model for semiconductor detector systems is proposed. According to the proposed model, a multistage cascade deconvolution IRS algorithm was developed using the C-R inverse system, R-C inverse system, and differentiator system. The silicon drift detector signals acquired from the analog-to-digital converter were tested. The experimental results indicated that the shaped pulses obtained using the proposed model had no undershoot, and the average peak base width of the output shaped pulses was reduced by 36% compared with that for a simple model proposed in a previous work [1]. Offline processing results indicated that compared with the traditional IRS algorithm, the average peak base width of the output shaped pulses obtained using the proposed algorithm was reduced by 11%, and the total elapsed time required for pulse shaping was reduced by 26%. The proposed algorithm avoids recursive calculation. If the sampling frequency of the digital system reaches 100 MHz, the proposed algorithm can be simplified to integer arithmetic. The proposed IRS algorithm can be applied to high-resolution energy spectrum analysis, high-counting rate energy spectrum correction, and coincidence and anti-coincidence measurements. Output-signal model Impulse response shaping C-R inverse system R-C inverse system Integer arithmetic Introduction 1 Semiconductor detectors are widely used for radiation measurements and nuclear analysis because of their high signal-to-noise ratios (SNRs) and high energy resolutions for rays and particles. Semiconductor detectors typically adopt reset-type charge-sensitive preamplifiers or R-C-type charge-sensitive preamplifiers. The semiconductor detector output is typically wide. In high-counting rate environments, the signals of semiconductor detectors accumulate significantly, resulting in counting loss and a low energy resolution. For coincidence measurements, it is necessary to obtain accurate time information of the signals. However, in high-counting rate environments, accurate time information of output signals is difficult to obtain, owing to large widths of the signals. For semiconductor detector systems, a high resolution and high counting rate are necessary for high-precision measurements. Digital pulse processing (DPP) systems are often adopted in semiconductor detector systems for signal processing and analysis [ 2 2 ]. Extensive research has been performed on digital systems for increasing the system resolution and counting rate. In research on digital systems, studies focusing on the output-signal model and the pulse-shaping algorithm have yielded interesting findings. Output-signal models have been proposed for describing the pulse shape. They play an important role in pulse shaping. Nakhostin et al. described the peak value of the output voltage pulse as an exponentially growing signal with a single decay time constant [ 3 3 ]. Mohammadian-Behbahani et al. proposed a two-component biexponential model for characterizing the preamplifier output pulses generated by an NaI (Tl) detector [ 4 4 ]. Födisch et al. developed a dual-exponential output-signal model with a single decay time constant for rectangular shaping [ 5 5 ]. Bogova et al. described the input signal in the digital domain as the product of a single exponential function and a Heaviside step function [ 6 6 ]. Kantor et al. proposed a simple model with three time constants to describe the pulse shapes generated by radiation detectors [ 1 1 ]. Khilkevitch et al. presented an analytical formula with three time constants to describe the pulse shape caused by a gamma quantum in a scintillation detector [ 7 7 ]. However, these output-signal models were presented without detailed explanations and have not been extensively studied. The impulse response shaping (IRS) algorithm is important for the development of high-precision measurement systems. Hong et al. proposed a unit IRS algorithm for counting-loss corrections in X-ray spectroscopy [ 8 8 ]. Liu et al. presented a dual-exponential IRS algorithm for counting-loss correction in X-ray spectroscopy [ 9 9 ]. Jordanov et al. developed efficient recursive algorithms that allow real-time pulse-shaping [ 10 10 ]. Imperiale et al. discussed pulse-shaping algorithms for high-energy semiconductor gamma-ray spectrometry [ 11 11 ]. Zhao et al. designed a novel digital filter based on a sinusoidal function [ 12 12 ]. Abbene et al. applied the classical single-delay line-shaping technique to dead-time corrections [ 13 13 ]. These algorithms are based on output-signal models with only one or two decay-time constants. The influence of output-signal models with more time constants on these IRS algorithms has not been discussed. Thuraka et al. realized a recursive algorithm in a field-programmable gate array (FPGA) with minimum resources to synthesize a trapezoidal output pulse from a step-input pulse [ 14 14 ]. Wen et al. proved that a pulse pile-up recovery algorithm based on template matching is effective for high-throughput gamma-ray spectroscopy [ 15 15 ]. Fernandes et al. developed a real-time algorithm for digitizer module FPGAs to calculate the amplitude of Gaussian-shaped pulses [ 16 16 ]. These digital solutions attempt to increase the resolutions and counting rates of semiconductor detector systems. However, they are based on complex mathematical operations and do not focus on the high-speed and parallel processing of real-time signals. In this study, the signal characteristics of semiconductor detectors were analyzed, taking silicon drift detectors (SDDs) as an example, and a new output-signal model of the semiconductor detector system was established. The new output-signal model and the simple model proposed in [ 1 1 ] were tested with acquired signals of the SDDs. The results indicated that the new model more accurately reflected the output signals of the semiconductor detector system than the simple model. Traditional IRS algorithms based on Z-transforms are both complex and recursive. Recursion increases the complexity of DPP systems and imposes restrictions on the speed of pulse shaping. A non-recursive multistage cascade deconvolution IRS (MCD-IRS) algorithm based on the new model is proposed in this paper. The proposed algorithm avoids recursive calculation. The pipeline schemes of the direct-form finite impulse response (FIR) filter can be implemented using this algorithm. As the sampling frequency of the digital system reaches 100 MHz, the algorithm can be simplified to integer arithmetic, which is suitable for implementation using FPGAs. The proposed algorithm was tested and analyzed offline with the acquired SDD signals. The results indicated that the average peak base width of the output shaped pulses obtained using this algorithm and the total elapsed time required for pulse shaping were significantly reduced compared with those for the traditional algorithm. The proposed output-signal model and IRS algorithm are important for the development of high-resolution energy spectrum measurement systems, coincidence measurement systems, anti-coincidence measurement systems, and high-counting rate correction systems. Semiconductor detection system for nuclear radiation 1 A digital detection system usually includes a semiconductor detector, a preamplifier, a front-end circuit, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a digital pulse processor, and computer software, as shown in Fig. 1 Fig. 1 . SDDs, which were proposed in 1984 by Gatti and Rehak, are high-resolution position-sensitive detectors for fast-ionizing particles and X-rays. The function of SDDs is similar to that of Si-PIN photodetectors. However, the electrode structure of SDDs differs from that of Si-PIN photodetectors [ 17 17 ]. SDDs have excellent properties, such as a high sensitivity, a high energy resolution, a high count rate, low electronic noise, a low leakage current, a high quantum efficiency, and a low capacitance [ 18 18 ]. The capacitance of the output electrode of the SDD is < 0.1 pF and is independent of the detector area. SDDs, which can be operated at room temperature without liquid nitrogen, are often used in X-ray analytical techniques, such as proton-induced X-ray emission, energy-dispersive X-ray spectroscopy, and X-ray fluorescence spectroscopy. They are the most commonly used detectors for X-ray spectroscopy. The front-end circuit is usually composed of a C-R circuit, a linear amplifier, and an offset adjustor. The C-R circuit shapes the output signal of the detector to an exponentially decaying pulse. The linear amplifier changes the amplitude of the exponentially decaying pulse [ 8 8 ]. The high-pass linear amplifier hardly changes the shape of the exponentially decaying pulse. The front-end circuit, which adopts high-pass linear amplifiers, can be simplified to a C-R circuit, which is referred to as the C-R system hereinafter. The amplified pulse is then sampled and quantized by the ADC, which follows the front-end circuit [ 19 19 ]. In most cases, the sampling frequency and quantization granularity significantly affect DPP. A digital pulse processor is generally composed of an FPGA and a microcontroller unit (MCU). The sampled pulse is processed in the FPGA and sent to the computer by the MCU. Methods 1 Output-signal model for semiconductor detector systems 2 An output-signal model for semiconductor detector systems was developed by analyzing the output signals of the SDDs, preamplifiers, and C-R differential circuits. Output signals of SDDs 3 In previous studies, the output signal of the charge-sensitive preamplifier was generally approximated as a step signal or an exponentially growing signal with a single time constant, and the signal output by the SDD was approximated as an impulse signal or an exponentially decaying signal with a single time constant [ 19 19 ]. With the development of digital systems, the sampling rate has been increased by high-speed ADCs, the amount of noise in semiconductor detector systems has been reduced, and the precision of the sampling has been improved. The rise time of a nuclear pulse can be accurately detected and described. Our experimental results indicated that the output signals of the SDDs should be approximated as dual-exponential signals, as shown in Fig. 2(a) Fig. 2(a) . The dual-exponential signal is defined as follows: <math display="block" id="M1"><mrow><mi>y</mi><mn>1</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mrow><mo>{</mo><mtable columnalign="left"><mtr><mtd><mn>0</mn><mo>;</mo></mtd></mtr><mtr><mtd><mi>A</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup><mo>−</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow><mo>)</mo></mrow><mo>;</mo></mtd></mtr></mtable></mrow><mtable><mtr><mtd><mrow><mi>t</mi><mo><</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mrow><mi>t</mi><mo>≥</mo><mn>0</mn></mrow></mtd></mtr></mtable><mo>,</mo></mrow></math> where A represents the pulse amplitude, and τ 2 and τ 3 represent the falling and rising parts of the pulse, respectively. Output signals of integral-reset-type charge-sensitive preamplifier 3 Charge-sensitive preamplifiers have low electronic noise, and the amplitudes of their output signals are hardly affected by parameters such as the interelectrode capacitance, open-loop input capacitance, and voltage gain. The preamplifiers adopted in high-resolution energy spectrum measurement systems are almost always charge-sensitive. Charge-sensitive preamplifiers include the resistance-feedback, direct-current (DC) optical-feedback, pulse optical-feedback, and integral-reset types. The circuit of the integral-reset-type charge-sensitive preamplifier used in digital systems is shown in Fig. 1 Fig. 1 . The transformation of an input signal into an output signal by an integral-reset-type charge-sensitive preamplifier is mathematically described as a convolution of the input signal <math id="M2"><mrow><mi>y</mi><mn>1</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow></math> and the unit step function <math id="M3"><mrow><mtext>ε</mtext><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow></math> . The convolution is expressed as <math display="block" id="M4"><mrow><mi>y</mi><mn>2</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>y</mi><mn>1</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>∗</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>.</mo></mrow></math> Eq. (2) can be rewritten as follows: <math display="block" id="M5"><mrow><mi>y</mi><mn>2</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mrow><mo>{</mo><mtable columnalign="left"><mtr><mtd><mn>0</mn><mo>;</mo></mtd></mtr><mtr><mtd><mi>A</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><mrow><mo>(</mo><mrow><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup><mo>−</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>+</mo><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>−</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mo>;</mo></mtd></mtr></mtable></mrow><mtable><mtr><mtd><mrow><mi>t</mi><mo><</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mrow><mi>t</mi><mo>≥</mo><mn>0</mn></mrow></mtd></mtr></mtable><mo>.</mo></mrow></math> The output signal of the integral-reset-type charge-sensitive preamplifier is shown in Fig. 2(b) Fig. 2(b) . C-R convolution transform of signals 3 The charge collected by the integral-reset-type charge-sensitive preamplifier increases with the accumulation of the detector output and DC bias, and it is not cleared until reset. The C-R differential circuit, as shown in Fig. 1 Fig. 1 , was adopted to process the output signal of the preamplifier. DC components were eliminated, and independent signals were obtained after the output signal was processed by the C-R differential circuit. The transfer function of the C-R differential circuit was obtained via analysis: <math display="block" id="M6"><mrow><mi>H</mi><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow><mo>=</mo><mfrac><mrow><msub><mi>V</mi><mi>o</mi></msub><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow><mrow><msub><mi>V</mi><mi>i</mi></msub><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow></mfrac><mo>=</mo><mfrac><mrow><mi>R</mi><mi>C</mi><mi>s</mi></mrow><mrow><mn>1</mn><mo>+</mo><mi>R</mi><mi>C</mi><mi>s</mi></mrow></mfrac></mrow></math> <math display="block" id="M7"><mrow><mi>H</mi><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow><mo>=</mo><mn>1</mn><mo>−</mo><mfrac><mn>1</mn><mrow><mi>R</mi><mi>C</mi><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac><mo>.</mo></mrow></math> In the time domain, the impulse response function of the C-R differential circuit is expressed as <math display="block" id="M8"><mrow><mi>H</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>δ</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>−</mo><mi>a</mi><mo>⋅</mo><msup><mi>e</mi><mrow><mo>−</mo><mi>a</mi><mi>t</mi></mrow></msup><mo>⋅</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>,</mo></mrow></math> where δ(t) is the unit impulse function and <math id="M9"><mrow><mi>a</mi><mo>=</mo><mfrac><mn>1</mn><mrow><mi>R</mi><mi>C</mi></mrow></mfrac></mrow></math> . Equation (6) is obtained by applying the inverse Laplace transform to Eq. (5). As indicated by Eq. (6), the impulse response function of the circuit is a linear combination of an exponentially decaying signal and unit impulse signal. The output signals of the integral-reset-type charge-sensitive preamplifier are processed by the C-R differential circuit, and the results are given by Eq. (7), where τ 1 = RC . <math display="block" id="M10"><mtable><mtr><mtd><mi>F</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>A</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup><mo>+</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mo>⋅</mo><mrow><mo>(</mo><mrow><mi>δ</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>−</mo><mfrac><mn>1</mn><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup><mo>⋅</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mtd></mtr></mtable></math> Equation (7) can be simplified to Eq. (8). The output signal of the C-R differential circuit is shown in Fig. 2(c) Fig. 2(c) . <math display="block" id="M11"><mtable><mtr><mtd><mi>F</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>A</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup><mo>+</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mo>⋅</mo><mrow><mo>(</mo><mrow><mi>δ</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>−</mo><mfrac><mn>1</mn><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup><mo>⋅</mo><mi>ε</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mtd></mtr></mtable></math> In the frequency domain, the output signals of the C-R differential circuit can be expressed by Eq. (9) using the Laplace transform. <math display="block" id="M12"><mrow><mi>F</mi><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow><mo>=</mo><mrow><mo>(</mo><mrow><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mi>s</mi></mfrac><mo>−</mo><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac><mo>+</mo><mfrac><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac></mrow><mo>)</mo></mrow><mo>⋅</mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>−</mo><mfrac><mn>1</mn><mrow><msub><mi>τ</mi><mn>1</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac></mrow><mo>)</mo></mrow></mrow></math> Eq. (9) can be rewritten as follows: <math display="block" id="M13"><mtable><mtr><mtd><mi>F</mi><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow><mo>=</mo><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac><mo>+</mo><mfrac><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac></mrow><mo>)</mo></mrow><mo>⋅</mo><mfrac><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>1</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac><mo>+</mo><mfrac><mrow><msub><mi>τ</mi><mn>1</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac></mtd></mtr><mtr><mtd><mo>⋅</mo><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac><mo>−</mo><mfrac><mrow><msub><mi>τ</mi><mn>1</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac><mo>⋅</mo><mfrac><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mi>s</mi><mo>+</mo><mn>1</mn></mrow></mfrac></mtd></mtr></mtable></math> Equations (8) and (10) are equivalent and express the output signals of the C-R differential circuit in the time and frequency domains, respectively. MCD-IRS algorithm 2 On the basis of the proposed output-signal model, an MCD-IRS algorithm is developed that comprises C-R inverse (INV_CR), R-C inverse (INV_RC), and differentiator (DIF) systems. The INV_CR system provides a digital realization method for inverse C-R differential circuit systems. The INV_RC system provides a digital realization method for inverse R-C integral circuit systems. Cascade IRS algorithm for the ideal dual-exponential pulse 3 Unit IRS methods for ideal dual-exponential pulses have been studied in attempts to find a digital solution to semiconductor detector systems. A three-stage cascade IRS (TCI) system, which is composed of INV_RC, INV_CR, and DIF systems, is designed to process the ideal dual-exponential pulse, as shown in Fig. 3 Fig. 3 . In Fig. 3 Fig. 3 , let the input signal of the INV_RC system be z[n], the output of the INV_RC system be y [ n ], the output of the INV_CR system be x[n] , and the output of the DIF system be p [ n ]. Then, the following equations are obtained: <math display="block" id="M14"><mrow><mi>y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>I</mi><mi>N</mi><mi>V</mi><mo>_</mo><mi>R</mi><mi>C</mi><mrow><mo>(</mo><mrow><mi>z</mi><mo stretchy="false">[</mo><mi>n</mi><mo stretchy="false">]</mo><mo>,</mo><mi>m</mi></mrow><mo>)</mo></mrow></mrow></math> <math display="block" id="M15"><mrow><mi>x</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>I</mi><mi>N</mi><mi>V</mi><mo>_</mo><mi>C</mi><mi>R</mi><mrow><mo>(</mo><mrow><mi>y</mi><mo stretchy="false">[</mo><mi>n</mi><mo stretchy="false">]</mo><mo>,</mo><mi>M</mi></mrow><mo>)</mo></mrow></mrow></math> <math display="block" id="M16"><mrow><mi>p</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>D</mi><mi>I</mi><mi>F</mi><mrow><mo>(</mo><mrow><mi>x</mi><mo stretchy="false">[</mo><mi>n</mi><mo stretchy="false">]</mo></mrow><mo>)</mo></mrow><mo>.</mo></mrow></math> The three-stage cascade IRS algorithm is derived via the following steps. The following equation is derived from the digital solution of the INV_RC system [ 20 20 ]: <math display="block" id="M17"><mrow><mi>y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>z</mi><mo stretchy="false">[</mo><mi>n</mi><mo stretchy="false">]</mo><mo>+</mo><mi>m</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><mi>z</mi><mo stretchy="false">[</mo><mi>n</mi><mo stretchy="false">]</mo><mo>−</mo><mi>z</mi><mo stretchy="false">[</mo><mi>n</mi><mo>−</mo><mn>1</mn><mo stretchy="false">]</mo></mrow><mo>)</mo></mrow><mo>,</mo><mi>m</mi><mo>=</mo><mfrac><mrow><mi>R</mi><mo>⋅</mo><mi>C</mi></mrow><mrow><mi>Δ</mi><mi>t</mi></mrow></mfrac><mo>.</mo></mrow></math> The following equation is derived from the digital solution of the INV_CR system [ 21 21 ]: <math display="block" id="M18"><mrow><mi>x</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mrow><mo>(</mo><mrow><mfrac><mn>1</mn><mi>M</mi></mfrac></mrow><mo>)</mo></mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow></mrow></mstyle><mo>+</mo><mi>y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>,</mo><mi>M</mi><mo>=</mo><mfrac><mrow><mi>R</mi><mo>⋅</mo><mi>C</mi></mrow><mrow><mi>Δ</mi><mi>t</mi></mrow></mfrac><mo>.</mo></mrow></math> The following equation is obtained from Eqs. (14) and (15): <math display="block" id="M19"><mrow><mi>x</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>+</mo><mi>m</mi><mo>⋅</mo><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow></mrow></mstyle></mrow><mi>M</mi></mfrac><mo>+</mo><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>+</mo><mi>m</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mi>z</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow></mrow><mo>)</mo></mrow><mo>.</mo></mrow></math> Equation (17) can be obtained by integrating both sides of Eq. (16). Equation (17) describes the digital signal transformation of a dual-exponential signal into a step signal in the form of digital integration. <math display="block" id="M20"><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>x</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow></mrow></mstyle><mo>=</mo><mrow><mo>(</mo><mrow><mfrac><mn>1</mn><mi>M</mi></mfrac></mrow><mo>)</mo></mrow><mo>⋅</mo><mrow><mo>(</mo><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mi>M</mi><mo>+</mo><mi>m</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>+</mo><mi>M</mi><mo>⋅</mo><mi>m</mi><mo>⋅</mo><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow></mrow></mstyle></mrow></mstyle></mrow></mstyle></mrow><mo>)</mo></mrow></mrow></math> The impulse signal is the first derivative of the step signal, that is, p ( n ) =x ( n )́; thus, Eq. (18) is obtained, which describes a three-stage cascade deconvolution IRS algorithm for an ideal dual-exponential pulse. <math display="block" id="M21"><mrow><mi>p</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mi>m</mi><mo>⋅</mo><mi>M</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mn>2</mn><mo>⋅</mo><mi>M</mi><mo>⋅</mo><mi>m</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>z</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>+</mo><mi>M</mi><mo>⋅</mo><mi>m</mi><mo>⋅</mo><mi>z</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow></mrow><mi>M</mi></mfrac></mrow></math> When the sampling rate of the digital system is sufficiently high, m and M in Eq. (18) can be approximated as integers. MCD-IRS algorithm for signals of semiconductor detector 3 The signals of the semiconductor detector, which are expressed by Eq. (8), can be deconvoluted into unit impulses step-by-step, as shown in Fig. 4 Fig. 4 . In Fig. 4 Fig. 4 , let the input signal of the INV_CR system be Y[n], the output of the INV_CR system be X[n] , the output of the DIF system be Z[n], and the output of the TCI system be P[n] . The MCD-IRS algorithm for the output signals of the semiconductor detector system can be derived as follows. In the first stage, the output signals pass through the INV_CR system to generate signals, as described by Eq. (3). The digital convolution of the INV_CR system is given as <math display="block" id="M22"><mrow><mi>X</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>k</mi><mo>⋅</mo><mstyle displaystyle="true"><mo>∑</mo><mrow><mi>Y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>+</mo><mi>Y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>,</mo><mi>k</mi><mo>=</mo><mfrac><mrow><mi>Δ</mi><mi>t</mi></mrow><mrow><mi>R</mi><mo>⋅</mo><mi>C</mi></mrow></mfrac></mrow></mstyle><mo>.</mo></mrow></math> In the second stage, the signals generated in the first stage are passed through the digital DIF system to generate the output signals expressed by Eq. (1). The digital solution for the DIF system is given by Eq. (20). <math display="block" id="M23"><mrow><mi>Z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mi>X</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow></mrow></math> In the third stage, the output signals of the DIF system are processed using the TCI system described by Eq. (18), and impulse signals are generated. The digital solution for the TCI system is given by Eq. (21). <math display="block" id="M24"><mrow><mi>P</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mi>m</mi><mo>⋅</mo><mi>M</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>Z</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mn>2</mn><mo>⋅</mo><mi>M</mi><mo>⋅</mo><mi>m</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>Z</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>+</mo><mi>M</mi><mo>⋅</mo><mi>m</mi><mo>⋅</mo><mi>Z</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow></mrow><mi>M</mi></mfrac></mrow></math> The digital solution expressed by Eq. (21) can be simplified to Eq. (22). Additionally, Eq. (22) can be simplified to Eq. (23), by setting K = 1 / k . Eqs. (22) and (23) express the digital solutions for semiconductor detector systems. <math display="block" id="M25"><mrow><mi>P</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mi>m</mi><mo>⋅</mo><mi>M</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>k</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>Y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow></mrow><mo>)</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mn>2</mn><mo>⋅</mo><mi>M</mi><mo>⋅</mo><mi>m</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>k</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>−</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow></mrow><mo>)</mo></mrow><mo>+</mo><mi>M</mi><mo>⋅</mo><mi>m</mi><mo>⋅</mo><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>k</mi></mrow><mo>)</mo></mrow><mo>⋅</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow><mo>−</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>3</mn></mrow><mo>]</mo></mrow></mrow><mo>)</mo></mrow></mrow><mi>M</mi></mfrac></mrow></math> <math display="block" id="M26"><mrow><mi>P</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mi>m</mi><mi>M</mi></mrow><mo>)</mo></mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mi>K</mi></mrow><mo>)</mo></mrow><mi>Y</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><mn>2</mn><mi>m</mi><mo>+</mo><mn>2</mn><mi>M</mi><mo>+</mo><mn>3</mn><mi>m</mi><mi>M</mi></mrow><mo>)</mo></mrow><mi>K</mi><mo>+</mo><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mn>2</mn><mi>m</mi><mi>M</mi></mrow><mo>)</mo></mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><mi>m</mi><mo>+</mo><mi>M</mi><mo>+</mo><mn>3</mn><mi>m</mi><mi>M</mi></mrow><mo>)</mo></mrow><mi>K</mi><mo>+</mo><mi>m</mi><mi>M</mi></mrow><mo>)</mo></mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow><mo>−</mo><mi>m</mi><mi>M</mi><mi>K</mi><mo>⋅</mo><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>3</mn></mrow><mo>]</mo></mrow></mrow><mrow><mi>M</mi><mo>⋅</mo><mi>K</mi></mrow></mfrac></mrow></math> In Eqs. (22) and (23), the result P [ n ] is only related to the input signal Y [ n ] and is unrelated to the intermediate calculation result. For designing a real-time signal-processing system using Eq. (22) or (23), high-speed pipeline schemes for parallel processing can be adopted. Experimental results and analysis 1 Experimental conditions 2 A FAST-SDD detector (XR-100SDD) [ 22 22 ] manufactured by Amptek was used in the experiments. XR-100 is a thermoelectrically cooled solid-state detector and a preamplifier. The detector was equipped with a reset-type preamplifier. The energy resolution of the detector was set as 125 eV. An X-ray tube with a Ag target was used to irradiate a Mn sample. The current of the X-ray tube was set as 8 μA, while the voltage was maintained at 35 kV. A vacuum pump was used for evacuation. The pressure was approximately 0.09 MPa. The ADC adopted in the digital system was operated at 20 Msps with a 12-bit resolution (AD9235). The acquired SDD signals, which were used for modeling and IRS in the experiments, were the original pulse data acquired from the ADC by sampling the amplified pulse of the linear amplifier. According to the following procedures, the acquired SDD signals were processed and shaped offline in the experiments. (1) Original pulse-data acquisition. (2) The time constants (τ 1 , τ 2 , and τ 3 ) for the output-signal model were obtained. According to the curve-fitting method, the time constants were obtained using the proposed output-signal model and the acquired SDD signals. (3) The constants ( m , M , k , and K ) for the proposed IRS algorithm were obtained. These constants were derived from the time constants of the output-signal model. (4) Impulse-response shaping. The acquired SDD signals were shaped into impulses using the MCD-IRS algorithm described by Eqs. (22) and (23). Comparison and analysis of output-signal models 2 Signal simulation and comparison 3 Equation (24), which was proposed in [ 1 1 ], describes the output signals of the semiconductor detector system in the time domain. <math display="block" id="M27"><mrow><mi>F</mi><mn>1</mn><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>B</mi><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup><mo>⋅</mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>−</mo><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow></mfrac><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup><mo>+</mo><mfrac><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow></mfrac><mo>⋅</mo><msup><mi>e</mi><mrow><mrow><mrow><mo>−</mo><mi>t</mi></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow><mo>)</mo></mrow></mrow></math> As indicated by Eq. (24), where B is a constant, the pulses have an exponentially decaying tail with a decay time of τ 1 . The decay time is determined by the electronic circuits of the preamplifier [ 1 1 ]. The leading-edge time τ 2 in Eq. (24) is determined by the integration time of the RC-CR filter of the preamplifier in the semiconductor detector system [ 1 1 ]. In Eq. (24), τ 3 represents the buildup time of the response pulse, which is consistent with the charge-collection time [ 1 1 ]. Eq. (24) also indicates that the output signal of the system can be obtained by multiplying the exponentially decaying signal by the output signal of the detector. In Eq. (24), <math id="M28"><mrow><msup><mi>e</mi><mrow><mo>−</mo><mrow><mi>t</mi><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup></mrow></math> can be generated by the convolution transform of the C-R differential circuit, and the other terms on the right-hand side of the equation are similar to the expressions in Eq. (3). Eq. (24) expresses a simple output-signal model for semiconductor detector systems. In the time domain, the signals given by Eqs. (8) and (24) almost coincided with the adjustment of τ 2 and τ 3 while τ 1 remained the same, as shown in Fig. 5(a) Fig. 5(a) . Additionally, in the frequency domain, the signals of the proposed and simple models coincided with the adjustment of τ 2 and τ 3 while τ 1 remained the same, as shown in Fig. 5(b) Fig. 5(b) . As shown in Fig. 5 Fig. 5 , the new model of the semiconductor detector system was similar to the output-signal model proposed in [ 1 1 ] in the time and frequency domains. The two models can both be used to simulate SDD signals for time–frequency analysis and have no significant differences. However, the experimental results indicated that there were differences between the models with regard to the unit IRS for SDD signals. Attempt on unit IRS 3 To test the output-signal model, a traditional unit IRS method was used. The traditional method is based on the Z -transform, which is described by Eq. (25). Here, V o ( z ) and V i ( z ) represent the Z -transforms of V o ( t ) and V i ( t ), which are the output and input signals of the semiconductor detector system, respectively. <math display="block" id="M29"><mrow><mi>H</mi><mrow><mo>(</mo><mi>z</mi><mo>)</mo></mrow><mo>=</mo><mfrac><mrow><msub><mi>V</mi><mi>o</mi></msub><mrow><mo>(</mo><mi>z</mi><mo>)</mo></mrow></mrow><mrow><msub><mi>V</mi><mi>i</mi></msub><mrow><mo>(</mo><mi>z</mi><mo>)</mo></mrow></mrow></mfrac><mo>=</mo><mfrac><mn>1</mn><mrow><msub><mi>V</mi><mi>i</mi></msub><mrow><mo>(</mo><mi>z</mi><mo>)</mo></mrow></mrow></mfrac></mrow></math> If V i ( t ) is defined by Eq. (24), Eq. (25) can be rewritten as follows: <math display="block" id="M30"><mrow><mi>H</mi><mrow><mo>(</mo><mi>z</mi><mo>)</mo></mrow><mo>=</mo><mfrac><mrow><mn>1</mn><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><msup><mi>z</mi><mrow><mo>−</mo><mn>1</mn></mrow></msup><mo>+</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>2</mn></msup><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><msup><mi>z</mi><mrow><mo>−</mo><mn>2</mn></mrow></msup><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>3</mn></msup><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><msup><mi>z</mi><mrow><mo>−</mo><mn>3</mn></mrow></msup></mrow><mrow><msub><mi>d</mi><mn>1</mn></msub><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mrow><mo>(</mo><mrow><mn>1</mn><mo>−</mo><msub><mi>d</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mo>+</mo><msub><mi>τ</mi><mn>3</mn></msub><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>3</mn></msub><mo>−</mo><mn>1</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow><msup><mi>z</mi><mrow><mo>−</mo><mn>1</mn></mrow></msup><mo>+</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>2</mn></msup><mrow><mo>(</mo><mrow><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><msub><mi>τ</mi><mn>3</mn></msub><msub><mi>d</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><msup><mi>z</mi><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></mfrac><mo>,</mo></mrow></math> Where <math id="M31"><mrow><msub><mi>d</mi><mn>1</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup></mrow></math> , <math id="M32"><mrow><msub><mi>d</mi><mn>2</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup></mrow></math> , and <math id="M33"><mrow><msub><mi>d</mi><mn>3</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow></math> , with T s being the sampling period. A digital solution for the signals of the semiconductor detector system in the time domain is given by Eq. (27), which is obtained from Eq. (26) using the inverse Z -transform. <math display="block" id="M34"><mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mi>X</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><mrow><mo>(</mo><mrow><mn>1</mn><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>+</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>2</mn></msup><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>3</mn></msup><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>3</mn></mrow><mo>]</mo></mrow><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><msup><mrow/><mn>2</mn></msup><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub><msub><mi>d</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow></mrow><mrow><msub><mi>d</mi><mn>1</mn></msub><mrow><mo>(</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub><mrow><mo>(</mo><mrow><mn>1</mn><mo>−</mo><msub><mi>d</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mo>+</mo><msub><mi>τ</mi><mn>3</mn></msub><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>3</mn></msub><mo>−</mo><mn>1</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mrow></mfrac></mrow></math> If V i ( t ) is defined by Eq. (8), the following digital solution can be obtained: <math display="block" id="M35"><mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>=</mo><mfrac><mrow><mi>X</mi><mrow><mo>[</mo><mi>n</mi><mo>]</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>1</mn></msub><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow><mo>]</mo></mrow><mo>+</mo><mrow><mo>(</mo><mrow><msub><mi>d</mi><mn>1</mn></msub><msub><mi>d</mi><mn>2</mn></msub><mo>+</mo><msub><mi>d</mi><mn>1</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub></mrow><mo>)</mo></mrow><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mi>X</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>3</mn></mrow><mo>]</mo></mrow><mo>−</mo><mrow><mo>(</mo><mrow><msub><mi>c</mi><mn>1</mn></msub><msub><mi>d</mi><mn>2</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>+</mo><msub><mi>c</mi><mn>2</mn></msub><msub><mi>d</mi><mn>1</mn></msub><msub><mi>d</mi><mn>3</mn></msub><mo>−</mo><msub><mi>c</mi><mn>3</mn></msub><msub><mi>d</mi><mn>1</mn></msub><msub><mi>d</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mi>Y</mi><mrow><mo>[</mo><mrow><mi>n</mi><mo>−</mo><mn>2</mn></mrow><mo>]</mo></mrow></mrow><mrow><msub><mi>d</mi><mn>1</mn></msub><msub><mi>c</mi><mn>3</mn></msub><mo>+</mo><msub><mi>d</mi><mn>2</mn></msub><msub><mi>c</mi><mn>3</mn></msub><mo>−</mo><msub><mi>d</mi><mn>1</mn></msub><msub><mi>c</mi><mn>2</mn></msub><mo>−</mo><msub><mi>d</mi><mn>2</mn></msub><msub><mi>c</mi><mn>1</mn></msub><mo>−</mo><msub><mi>d</mi><mn>3</mn></msub><msub><mi>c</mi><mn>1</mn></msub><mo>−</mo><msub><mi>d</mi><mn>3</mn></msub><msub><mi>c</mi><mn>2</mn></msub></mrow></mfrac><mo>,</mo></mrow></math> where <math id="M36"><mrow><msub><mi>d</mi><mn>1</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>1</mn></msub></mrow></mrow></mrow></msup></mrow></math> , <math id="M37"><mrow><msub><mi>d</mi><mn>2</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>2</mn></msub></mrow></mrow></mrow></msup></mrow></math> , <math id="M38"><mrow><msub><mi>d</mi><mn>3</mn></msub><mo>=</mo><msup><mi>e</mi><mrow><mo>−</mo><mrow><mrow><msub><mi>T</mi><mi>s</mi></msub></mrow><mo>/</mo><mrow><msub><mi>τ</mi><mn>3</mn></msub></mrow></mrow></mrow></msup></mrow></math> , <math id="M39"><mrow><msub><mi>c</mi><mn>1</mn></msub><mo>=</mo><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><mfrac><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac><mo>+</mo><mfrac><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac></mrow></math> , <math id="M40"><mrow><msub><mi>c</mi><mn>2</mn></msub><mo>=</mo><mfrac><mrow><msub><mi>τ</mi><mn>1</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>2</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>2</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac></mrow></math> , and <math id="M41"><mrow><msub><mi>c</mi><mn>3</mn></msub><mo>=</mo><mfrac><mrow><msub><mi>τ</mi><mn>1</mn></msub><mo>⋅</mo><msub><mi>τ</mi><mn>3</mn></msub></mrow><mrow><msub><mi>τ</mi><mn>3</mn></msub><mo>−</mo><msub><mi>τ</mi><mn>1</mn></msub></mrow></mfrac></mrow></math> , with T s being the sampling period. The SDD signals obtained from the ADC were tested via Eqs. (27) and (28), that is, using the simple and new models, respectively, and the results are shown in Fig. 6 Fig. 6 . As shown in Fig. 6(a) Fig. 6(a) , the unit impulses of the SDD signals obtained using the simple model oscillated. Fig. 6(a) Fig. 6(a) also indicates that the undershoots of the pulses were large. Longer tails appeared after the pulse undershoots were eliminated by adjusting τ 1 , τ 2 , and τ 3 , as shown in Fig. 6(c) Fig. 6(c) . The tailing phenomenon is attributed to the fact that the output-signal model described by Eq. (24) lacks the support of a physical model. The output signal expressed by Eq. (24) is the product of two signals with clear physical meaning. In a linear system, one signal cannot be directly multiplied by another signal. As shown in Fig. 6(b) Fig. 6(b) , the shaped pulses obtained using the new model had no undershoot. Fig. 6(c) Fig. 6(c) presents the results for the two shaping methods. The unit impulse obtained using the new model was narrower than that obtained using the simple model. Additionally, the unit impulse obtained using the new model had a shorter tail, while the noise remained at the same level. It can be concluded that the new model outperformed the simple model for processing overlapping signals. Quantitative comparison of output-signal models 3 Typically, the total full width at half maximum (FWHM) of the peaks is used to evaluate digital pulse shapers [ 23 23 , 24 24 ]. However, there are several other methods for comparing unit IRS algorithms. In this study, two methods were employed: comparing the average peak base widths of the impulses and comparing the total areas of the impulses (a smaller total area corresponds to better unit IRS). The SDD signals were tested using the two output-signal models. After adjustment of τ 1 , τ 2 , and τ 3 , the average amplitudes of the impulses obtained using the two models were essentially identical. The experimental results indicated that the total FWHMs and SNRs obtained using the two models had no significant differences. However, the average peak base widths of the output shaped pulses obtained using the simple and new models were 6.017 × 50 ns and 3.793 × 50 ns, respectively; that is, the average peak base width was 36% smaller for the proposed model. Let the area of the impulse obtained using the new model be A n and the area of the impulse obtained using the simple model be A s . Then, ∑ A n and ∑ A s represent the total areas of the impulses obtained using the two models. SDD signals with a length of 1000 were tested. The value of ∑ A n was 1.459× 10 5 , the value of ∑ A s was 1.727× 10 5 , and the value of <math id="M42"><mrow><mrow><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><msub><mi>A</mi><mi>n</mi></msub></mrow></mstyle></mrow><mo>/</mo><mrow><mstyle displaystyle="true"><mo>∑</mo><mrow><msub><mi>A</mi><mi>s</mi></msub></mrow></mstyle></mrow></mrow></mrow></math> was 84%. Additionally, for the simple model, small pseudo-peaks appeared on tails when the SDD signals overlapped significantly. Pseudo-peaks result can in pulse-counting rate errors. The results indicated that the new output-signal model described by Eq. (8) agreed better with the output SDD signals than the simple model proposed in [ 1 1 ]. Test and analysis of MCD-IRS algorithm 2 The acquired SDD signals were tested using the MCD-IRS algorithm, and the results are shown in Fig. 7 Fig. 7 . As shown in Fig. 7(a) Fig. 7(a) , the width of the TCI output impulse was between 1 and 4 sampling points, the undershoots of the pulses were eliminated, and the shaped pulses had almost no tails. As indicated by Fig. 7(b) Fig. 7(b) , the MCD-IRS algorithm stably processed SDD signals at high counting rates. In the experiments, 2 MB of acquired SDD signals were processed and shaped offline. The personal computer used in the experiments was equipped with an Intel CPU (i5-6200U) with 16 GB of random-access memory. The experimental results indicated that the average peak base widths of the output shaped pulses obtained using the traditional and new IRS algorithms were 3.793 × 50 ns and 3.363 × 50 ns, respectively; i.e., the average peak base width was 11% smaller for the proposed algorithm. The numbers of impulses obtained using the traditional and new algorithms were 29970 and 30004, respectively. The total elapsed time required for pulse shaping was 0.23 and 0.17 s for the traditional and new algorithms, respectively; i.e., the total elapsed time required for pulse shaping was 26% shorter for the proposed algorithm. Offline processing results for the acquired SDD signals indicated that the digital solution described by Eq. (22) or (23) is consistent with the solution described by Eq. (28). Equation (28), which was obtained using the Z -transform and inverse Z -transform, contains the recursive term Y [ n -2] on the right-hand side. This term indicates that the result of each calculation depends on the previous calculation result. Owing to the noise and background in measured signals, there are errors in the calculations. These errors may accumulate and be transferred in calculation processes, affecting the output signals of the semiconductor detector system. Recursion increases the complexity of DPP systems. In DPP systems, a feedback network should be included owing to the recursive term. The feedback network affects DPP in high-speed and real-time systems. In the DPP system based on Eq. (28), signals can only be processed serially. The filter implemented using Eq. (28) is an infinite impulse response filter, which has parasitic oscillation in some cases. In the implementation of the MCD-IRS algorithm, attention should be paid to multiple solutions to inverse systems. Multiple solutions may result in instability of the inverse system. For example, the MCD-IRS algorithm was unstable in the INV_CR system when processing signals whose baseline was not zero. However, when there was a direct series connection between the INV_CR and DIF systems, the MCD-IRS algorithm was stable. Figs. 3 Figs. 3 and 4 4 show a scheme for developing a stable algorithm based on the direct series connection between the INV_CR and DIF systems. In tasks that use short word-length integers or fixed-point data, FPGAs exhibit a high degree of parallelism. However, FPGAs cannot achieve the optimum performance in high-precision floating-point arithmetic operations [ 25 25 , 26 26 ]. If the sampling rate of the digital system is sufficiently high, the sampling frequency can reach 100 MHz. In Eqs. (18) and (23), m, M, and K can be approximated as integers. Because the native data from the ADCs are integers, the algorithm can be simplified to integer arithmetic, which is suitable for implementation with FPGAs. Pipelining is widely used in DPP systems to accelerate digital signal processing [ 27 27 ]. The main problem with conventional pipelining is that it is based on the propagation delay information [ 27 27 ]. The MCD-IRS algorithm is non-recursive; therefore, a pipeline scheme of the direct-form FIR filter can be implemented. Conclusion 1 An output-signal model and a non-recursive IRS algorithm for the signals of semiconductor detector systems were proposed. The output-signal model was developed according to an analysis of the detector output signal-processing flow. It was tested and analyzed using the acquired SDD signals. The experimental results indicated that the average peak base width of the output shaped pulses obtained using the new model was reduced by 36% compared with that for the simple model proposed in [ 1 1 ]. The undershoots of the shaped pulses were eliminated, and the shaped pulses had almost no tails. Compared with the simple model, the new output-signal model agreed better with the output SDD signals and was more stable when shaping the SDD signals into unit impulses. On the basis of the new model, an MCD-IRS algorithm is proposed. The new IRS algorithm was implemented using INV_RC, INV_CR, and DIF systems. Offline processing results for acquired SDD signals indicated that compared with the traditional IRS algorithm based on the Z-transform, the average peak base width of the output shaped pulses obtained using the new algorithm was reduced by 11%, and the total elapsed time required for pulse shaping was reduced by 26%. The proposed algorithm avoids recursive calculation. Pipeline schemes can be used to implement new algorithms. When the sampling rate of the digital system is sufficiently high, the algorithm can be simplified to integer arithmetic, which is suitable for implementation with FPGAs. The new non-recursive IRS algorithm is more suitable than the traditional algorithm for high-speed parallel processing of the acquired SDD signals. In high-counting rate environments, pulses overlap significantly, e.g., in the case of real-time online detection of industrial material compositions or rapid analysis of alloys. The MCD-IRS algorithm can be applied in these cases. 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All authors read and approved the final manuscript. 10.1007/s41365-022-01027-9 This work was supported by the National Natural Science Foundation of China (Grant Nos. 11975060, 12005026, and 12075038), the Major Science and Technology Project in Sichuan Province (Grant No. 19ZDZD0137), and the Sichuan Science and Technology Program (2020YFG0019). 2021-12-14 2022-02-28 2022-03-03 2022-04-20 2022-11-30 © China Science Publishing & Media Ltd. (Science Press), Shanghai Institute of Applied Physics, the Chinese Academy of Sciences, ChineseNuclear Society and Springer Nature Singapore Pte Ltd. 2022 This is a post-peer-review, pre-copyedit version of an article published in Nuclear Science and Techniques. The final authenticated version is available online at: http://dx.doi.org/10.1007/s41365-022-01027-9 http://dx.doi.org/10.1007/s41365-022-01027-9 . 2022 Nuclear Science and Techniques 04 33