Characteristic Curve of the Clamp Diode at the Input Port

The power-clamp data within the IBIS model describe the voltage–current relationship of the input port when input voltage V_in surpasses the component supply voltage VCC. During this period, as shown in Fig. 3a, the input port ground-clamp diode reverses the cutoff, whereas the power supply clamps the positive conduction of the diode.

Fig. 3Full-screen View

Schematic of the V-I characteristic curve extraction of the component for the (a) power Clamp, (b) GND clamp, (c) pullup, and (d) pulldown

Given that the reverse current of the diode is significantly smaller than its forward conduction current and that the input buffer inverter-gate leakage current is negligible, it can be assumed that this dataset corresponds to the V-I characteristic curve of the power-supply clamp diode. Notably, the IBIS model indicates that voltage V_table within the power-clamp data table adheres to the following relationship: $V_{\text{table}}=\text{VCC}-V_{\text{in}}\mathrm{,}$ (1) where VCC is the power supply voltage and V_in is the voltage of the input pin. When analyzing the V-I characteristics of a power supply clamp diode, the corresponding voltage V should be obtained using the following transformation: $V=V_{\text{in}}-\text{VCC}=-V_{\text{table}}.$ (2) Similarly, the GND Clamp refers to the voltage of the input pins and current characteristics when the input voltage is below the GND level. During this moment, the power-clamp diode reverses, and the ground-clamp diode conducts positively (Fig. 3b). Consequently, the GND Clamp data represent the V-I characteristic curve of the ground-clamp diode. Voltage V_table in the GND Clamp data table has the following relationship according to the IBIS model: $V_{\text{table}}=V_{\text{in}}-V_{\text{GND}}\mathrm{,}$ (3) where V_GND is the voltage of the ground; thus, to extract the V-I characteristics of the ground-clamp diode, voltage V must be obtained using the following transformation: $V=V_{\text{GND}}-V_{\text{in}}=-V_{\text{table}}.$ (4)

Characteristic Curve of the Transistor at the Output port

The driver inverter and ESD-protection circuit are the major components of the output port of the digital component. Different types of output buffers exist, such as push-pull, I/O, and open-drain buffers. Each buffer type has a different circuit structure and function. Consequently, the V-I curves for the different buffer types differ; an illustration of the fundamental push–pull output is presented along with an explanation of methods to extract the transistor characteristic curve for the port circuit. Notably, this extraction approach is also applicable to other buffer types with minor modifications, as required.

The pullup curve shows the voltage–current relationship of a pin when the output state was set at one. The pull-up PMOS is enabled at this time, whereas the pulldown NMOS is disabled. A scan voltage in the range of -VCC to 2 VCC was applied to the output pin to obtain the voltage–current relationship. According to the IBIS model, voltage V_table, described in the pullup datasheet, is defined as $V_{\text{table}}=\text{VCC}-V_{\text{out}}\mathrm{.}$ (5) To extract the output characteristics of the pullup PMOS, the V-I data must be obtained inside the -VCC to VCC range of the output pin voltage V_out, which corresponds to the 2 VCC to 0 V interval of the pullup curve. Figure 3c shows the state of the output port during this period.

In addition, the IBIS output-buffer model pulldown data can be used to determine the pulldown curves of NMOS and power-clamp diodes. The pulldown curves show the relationship between the voltage and current of the pin when the output state is set at zero. During this period, the pullup PMOS was disabled, and the pulldown NMOS was enabled. Subsequently, scan voltages ranging from -VCC to 2 VCC were applied to the output pin. The voltage–current relationship was determined for the output pin. The data between 0 and 2 VCC is captured on the Pulldown curve. The voltage and current at the output pin were observed at this stage, as shown in Fig. 3d.

Extract Model Parameters of Clamp Diode

In the previous section, we discussed a method for obtaining the electrical characteristics of transistors using the IBIS model. The following section focuses on the method for selecting a suitable physical model of the transistor for parameter extraction.

The model equation for a diode based on semiconductor physics [31] can be expressed as follows: $I_{\text{D}}=I_{\text{s}}\left(e^{\frac{V_{\text{D}}}{n{V}_{\text{T}}}}-1\right)\mathrm{,}$ (6) where I_s represents the reverse-saturation current with a typical value ranging from 10×10^-6 A to 20×10^-6 A; V_D is the junction voltage, which equals the diode terminal voltage minus the parasitic resistance drop; V_T is the thermal voltage constant with a typical value of 25.8 mV at 25 ℃; and n represents the emission coefficient.

The reverse-saturation current I_s, emission coefficient n, and parasitic resistance R govern the DC behavior of a diode. Modeling only the essential parameters while leaving the other parameters at their default values is acceptable.

To obtain the values of the parasitic resistance R, emission coefficient n, and reverse-saturation current I_s, reference point coordinates were first selected from the forward characteristic curve of the diode. These coordinates were substituted into Eq. (6), to determine the parameter values.

In this study, a classic digital component CMOS non-inverting multiplexer, NC7SZ157, was used as an example to demonstrate the modeling process. The golden parameter values of the diode for NC7SZ157 were obtained, as listed in Table 1, using the diode characteristic parameter-extraction technique along with a datasheet search. These values were established as a part of this study. Notably, when analyzing the IBIS model of NC7SZ157, the power-clamp diode was not included. Therefore, only the ground-clamp diodes are listed in Table 1. The input model parameters for the TID effect were extracted using the same method based on measured IBIS experimental data.

Extract Model Parameters of a MOSFET

(i) Threshold Voltage V_th

The threshold voltage is the turning point for the formation of the inverse layer of the MOS component, and a conduction channel is formed when the gate voltage is greater than the threshold voltage. Numerous methods for extracting the MOSFET threshold voltage exist, such as the line extraction, constant current, leakage current second-order derivative, transconductance extraction, Y-function, and beta-function methods [32, 33]. In this study, the linear extrapolation method was chosen for threshold voltage extraction because of its suitability for components with different channel lengths and its potential to make full use of the transistor output characteristics.

The linear extrapolation method is based on the principle that when V_ds is small, the MOSFET output characteristics can be expressed as $I_{\text{ds}}=\frac{W{\mu }_{\text{n}}{C}_{\text{ox}}}{L}\left(V_{\text{gs}}-V_{\text{th}}\right)V_{\text{ds}}\mathrm{,}$ (7) where W is the gate width, μ_n is the carrier mobility, C_ox is the capacitance of the gate-oxide unit area, and L is the gate length. For a given V_ds drain current I_ds depends linearly on gate voltage V_gs. The straight line with the steepest slope can be identified by extrapolating the component transfer characteristics. The intersection of this line with the horizontal axis (V_gs) indicates the threshold voltage. The reason for choosing the point with the maximum slope is that the subthreshold current dominates the curve when V_gs is small, whereas the carrier mobility decreases with increasing gate voltage when V_gs is large.

(ii) Saturation Voltage V_sat, Saturation Current I_sat, Conductance Parameter K_n and Channel-length Modulation Coefficient V_A

When the MOSFET operates in the linear region, the relationship between the drain voltage and the current is as follows [10]: $I_{\text{ds}}=\frac{W{\mu }_{\text{n}}{C}_{\text{ox}}}{2L}\left(2\left(V_{\text{gs}}-V_{\text{th}}\right)-A_{\text{bulk}}{V}_{\text{ds}}\right)\frac{V_{\text{ds}}}{1+\frac{V_{\text{ds}}}{L{E}_{\text{c}}}}\mathrm{,}$ (8) where A_bulk is the body charge effect coefficient and E_c is the critical electric field for velocity saturation.

To extract the values of the saturation voltage V_sat, saturation current I_sat, Conductance Parameter K_n, and channel-length modulation coefficient V_A, the reference point coordinates are selected from the linear region of the output characteristic curve of the MOS transistor. These coordinates were substituted into Eq. (8) to obtain parameter values.

Consequently, the parameters associated with the short-channel model of the MOSFET were successfully extracted. The extracted NC7SZ157 output buffer golden model parameters are listed in Table 2 (V_gs = 3.3V). The output model parameters for TID effect were extracted using the same method, based on the measured IBIS experimental data.

Effect of Ionizing Radiation on the Electrical Properties of MOS Components

The TID effect causes two types of charge traps to form within the oxide of the MOS components [34, 35]: fixed oxide charge (Not) and interface-trapped charge (Nit). These charges are responsible for changes in the electrical behavior of the components, resulting in a number of events, such as threshold voltage drift and carrier mobility degradation.

According to recent studies, the threshold voltages of NMOS and PMOS tend to decrease with increasing TID. However, NMOS exhibits a rebound effect at higher doses [36]. In addition, the TID effect results in a decrease in the carrier mobility of the MOS device and, hence, a decrease in transconductance. Because of the profound effect of carrier mobility attenuation on the MOS device transconductance and current-handling capability, this effect requires careful consideration when analyzing the TID effects of MOS devices [37, 35].

Changes in the threshold voltage and carrier mobility can affect the conduction resistance of the transistor at the output of the component, increasing the conversion time. This occurs during a rising-edge transition when the NMOS transistor is gradually turned off and the PMOS transistor is gradually turned on. The conversion time of the waveform is related to the conduction resistance of the PMOS transistor and size of the load capacitor. The TID effect causes a negative drift in the threshold voltage of the PMOS and a decrease in the channel carrier mobility, that is, an increase in the on-state resistance, which leads to an increase in the time constant of the RC circuit formed by this equivalent resistance, port parasitic or load capacitance, and a longer rise time. During a falling-edge transition, the PMOS transistor gradually turns off, the NMOS transistor gradually turns on, and the parasitic or load capacitance is discharged through the NMOS transistor. TID irradiation can cause both the threshold voltage and carrier mobility of the NMOS transistor to decrease, and because the effect of the two on the conduction resistance is opposite, their mutual canceling effect results in a less pronounced change in the falling-edge waveform compared to the PMOS transistor with varying TID.

Behavior–Physical Hybrid Model of CMOS Digital IC

In this study, a CMOS noninverting multiplexer, NC7SZ157, was used as a case study to illustrate the process of creating a hybrid model, as shown in Fig. 1b and Fig. 2. The gold functional area, input buffer, and output buffer models of NC7SZ157 were developed as the first steps of this process.

(i) Modeling of Functional Area

The functional domain of the behavioral-physical model of the hybrid digital IC pertains to the description of the logic function of the component being investigated along with its digital behavior. The complexity of this module varies, depending on the function and size of the device being studied. Constructing the model as a separate and callable module facilitates ease of readability and future modifications, which is highly recommended.To illustrate the efficacy of this concept, the paper employed the NC7SZ157 datasheet to describe the functional area in VHDL, as indicated in Alg. 1. The input ports in Alg. 1 are denoted as S, I₀, and I₁, respectively. In contrast, Z denotes the output port of NC7SZ157.

(ii) Modeling of Input Port

Based on the model parameters in Table 1, a physical model of the input port for the NC7SZ157 was designed using VHDL-AMS, as shown in Alg. 2.

(iii) Modeling of Output Port

The physical model of the output port for NC7SZ157 was designed using VHDL-AMS, as shown in Alg. 3, based on the model parameters listed in Table 1.

The functional area should be combined with the input and output port models to form a golden model of the component. Figure 4a shows the simulation results of the golden model using the SystemVision software. The golden delay can be obtained from the component datasheet (the propagation delays I₀, I₁ and S to Z are 3.2 ns). The propagation delay is defined as the measurement starting when 50% of the rising or falling edge of the input signal arrives and ending when 50% of the rising or falling edge of the output signal is reached, as shown in Fig. 4. The simulation parameters are as follows: the input I₀ is set to state ‘0’, I₁ is set to state ‘1’, the input clock is set to 50 MHz, and the output load is set to 1 kΩ. A comparison of the datasheet and simulation results confirms that the logic function of the developed model is accurate, and that the model is capable of reproducing the analog electrical characteristics of the port.

Fig. 4Full-screen View

Simulation results for NC7SZ157 of (a) Golden model; (b)Time degradation caused by TID effect

Time Degradation Modeling

To accurately simulate the impact of the TID on digital combinatorial and sequential logic, timing degradation must be considered, which can cause changes in circuit propagation delay and even disrupt the sequential logic function. As shown in Alg. 4, it is necessary to reconstruct the functional domain of the hybrid model and introduce a pin-to-pin signal propagation delay to model the propagation delay.

In Algorithm 4, delay I₁, delay I₀, and delay s are introduced as three parameters representing the pin-to-pin signal propagation delay from input ports I₁, I₀, and S to output port Z. The preradiation delay can be obtained from the component data. TID experiment results show that the propagation delay of NC7SZ157 in S-Z path is 3.2 ns at 0 krad(Si), 3.9 ns at 50 krad(Si) and 4.3 ns at 100 krad(Si). The simulation results are presented in Fig. 4b.

From Fig. 4b it is clear that the signal transmission delay gradually increases as the TID increases. It can be concluded that the above model accurately represents the radiation-induced timing degradation of the component. Therefore, the proposed modeling method presented in this paper is feasible.

Modeling TID Effect of Output Port

The effect of the TID on the output port can be modeled by considering two key factors: the TID-induced effect on the threshold voltage and the carrier mobility of the port transistor, as described in the Introduction section of this chapter, on the effect of the TID on digital devices. To demonstrate the feasibility of this modeling approach, a CMOS output inverter circuit was constructed, as shown in Fig. 5a, in the SystemVision simulation environment.

Fig. 5Full-screen View

Schematic of (a) inverter circuit for CMOS and (b) Simulation result of (a)

In Fig. 5a the load capacitance C1 and resistance R1 were as 2 pF and 1 KΩ respectively. The simulation results are shown in Figs. 5b show that the electrical characteristics of the pull-up PMOS can be changed by adjusting the threshold voltage and carrier mobility. The conduction cases one–four reflect an increase in the threshold voltage of the PMOS and a decrease in the carrier mobility of the PMOS. It can be observed that, with an increase in the threshold voltage and a decrease in the carrier mobility of the pull-up PMOS, the PMOS on-resistance increases, leading to an increase in the rise time of the level at the output pin V_out and a decrease in the high-level amplitude. Therefore, the inclusion of the TID effect of the output pin threshold voltage of the transistor and carrier mobility in the model allows for the representation of the TID-related variation in the CMOS device port characteristics.

Figure 5b are intended to verify the TID effect modeling method, in which the threshold voltage (V_th) and conductance parameters (K_n) are added to the port. During the modeling of the TID effect, the threshold voltage (V_th) and conductance parameter (K_n) of the device at different dose points were extracted by measuring the transfer characteristic curve of the transistor at the port of the TID experiment. Subsequently, the extracted V_th and K_n are used as generic parameters for Alg. 3 to obtain simulation results for the TID effect at the port, as shown in Fig. 7.

Fig. 7Full-screen View

Comparison of experiment results with simulation results at (a) 0 krad(Si); (b) 50 krad(Si) and (c) 100 krad(Si)