A CMOS front-end integrated circuit consisting of 16 identical analog channels is proposed for semiconductor radiation detectors. Each of the 16 channels has a low noise charge sensitive amplifier, a pulse shaper, a peak detect and hold circuit and a discriminator, while analog voltage and channel address are routed off the chip. It can accommodate both electron and hole collection with selectable gain and peaking time. Sequential and sparse readout, combining with self-trigger and external trigger, makes four readout modes. The circuit is implemented in a 0.35 μm DP4M (double-poly-quad-metal) CMOS technology with an area of 2.5×1.54 mm² and power dissipation of 60 mW. A single channel chip is tested with Verigy 93000. The gain is adjustable from 13 to 130 mV·fC^–1 while the peaking time varies between 0.7 and 1.6 μs. The linearity is more than 99% and the equivalent noise charge is about 600e.