1.1. Background and physical objective

The Large High-Altitude Air Shower Observatory (LHAASO) is oriented to study and observe the high-energy cosmic rays of the universe. It consists of several detector systems: a 1-km² complex array; a wide FOV Cherenkov telescope array; a 100-m² high threshold core-detector array; and a 90000-m² water Cherenkov detector array (WCDA) [1]. The WCDA is one of major components of the LHAASO project [2,3],which consists of four 150 m × 150 m water ponds. As shown in Fig. 1, each pond is divided into 30 × 30 cells, and each cell has one photomultiplier tube (PMT) facing upwardtoward the bottom center of the cell to collect the Cherenkov light produced by the shower particles in water [4].

Fig. 1Full-screen View

(Color online) WCDA in LHAASO project.

Figure 2 illustrates an air shower detected by the PMTs in the WCDA. The kernel task of the WCDA has two jobs: (1) the time measurement of secondary particles is used to determine the incidence direction of the air shower; and (2) the charge measurement is used to obtain particle identification and energy information.

Fig. 2Full-screen View

(Color online) Block diagram of the Gamma ray detected by the PMT.

1.2. Requirements

According to the application requirements and performance of the detectors, Table 1 lists the WDCA readout electronics. To target the research purpose, the amount of the Cherenkov light (corresponding to the charge information of the PMT output signal) and its arrival time on the PMTs both need to be measured efficiently. The amplitude of the smallest signal, 1 photo electron (P.E.), is as low as 60 μA, with a leading edge of 4 ns, and a trailing edge of 16 ns. A large dynamic range from 1 P.E. to 4000 P.E. (0.75 pC to 3000 pC) is required. The charge measurement requirement is equivalent to an effective number of bits of around 13.3 bit of analog-to-digital-converter.

To simplify the structure of the front end electronics, a front-end readout for an application-specific integrated circuit (ASIC) is designed. The PMT signal is imported to the leading-edge discrimination circuit for time measurement, and then is converted to a pulse width for charge-to-time conversion based on the time-over-threshold method. A test system is designed to evaluate the performance of this ASIC. The output of the ASIC is fed to a field programmable gate array (FPGA)-based time-to-digital converter (TDC) for digitization, and then the resulting data are read through a universal serial bus (USB) interface.

1.3. State-of-the-art applications

We investigated this method using similar time digitization systems. Their performance is listed in Table 2.

Compared with ASIC-based TDC, the FPGA-based TDC reduces system complexity while also providing good flexibility [10], because the TDC and control logic, as well as the data-transferring interface, can be integrated within a single FPGAdevice. As for the FPGA-based TDCs, the time resolution for a counter-based method is limited. With the interpolation method using special delay cells in the FPGAs, time resolution can be greatly improved. In particular, when using the wave union technique, a resolution of 10 ps was successfully achieved. Because special resources are needed, the high cost for logic consumption is problematic. This paper aims to design an FPGA-based TDC with a bin size of around 330 ps and low resource consumption (presented in Sec.3.2).

3.1. Serial interface logic design for ASIC configuration

The I²C protocol is used widely in ASIC configuration, considering the following advantages: the validity of data transfer is guaranteed by the acknowledgment process, different registers can be accessed by addresses, and all I²C devices are designed to communicate on the shared two-wire bus (i.e., featuring a simple structure).

We designed an I²C interface logic to configure the ASIC chip and other peripheral devices on the front-end module. The structure of the Algorithmic State Machine (ASM) is shown in Fig. 6. The logic was designed with Verilog Hardware Description Language on Quartus® II 13.1 and was implemented on an Intel® (Santa Clara, CA) FPGA EP3C55F780 (formerly Altera; San Jose, CA).

Fig. 6Full-screen View

ASM figure of I²C interface.

To confirm the logic functionality, we conducted simulations. Figure 7 shows the functional simulation results of the three wire signals, including the serial data (SDA, containing addresses and data), serial clock (SCL), and the write start (WR) signal, which agree with the expected results. As shown in Fig. 7, a HIGH to LOW transition on the SDA line, while SCL is HIGH, acts as a START signal, whereas a LOW to HIGH transition on the SDA line, while SCL is HIGH, acts as a STOP signal. The receiver is obliged to generate an acknowledgment (“Ack1, 2, 3, 4” in Fig. 7) after each byte is received. In Fig. 7, a total of four bytes are transferred successfully in the simulation. The first byte contains the address of the receiver, whereas the following three bytes include the user command and data information.

Fig. 7Full-screen View

(Color online) Simulation result of I²C timing diagram: SCL (serial clock), WR (write start), and SDA (serial data containing addresses and data). The SCL and SDA communicate on the shared two-wire bus.

3.2. TDC integrated in the FPGA

To digitize the output signals from the ASIC, we designed a TDC based on an FPGA and time interpolation method [12]. The designed logic about TDC is implemented in an Intel® FPGA EP3C55F780.

Figure 8 shows the block diagram of this TDC. It consists of a coarse-time counter and a fine-time measurement stage. The coarse counter is used to record the high bits of the time measurement result, with a clock (CLK_SYS) frequency of 62.5 MHz. The fine-time measurement is used to obtain the low bits, with an 8-phase clock (fanned out by an interval phase-locked loop with a 45° phase interval), and a frequency of 375 MHz (equivalent to 3 GHz). The 26-bit coarse counter achieves a measurement range of 1.0737 s, whereas the 6-bit fine measurement corresponds to the TDC bin size of 333 ps. The encoded 6-bit fine-time measurement result and the 26-bit coarse counter output constitute a final 32-bit time measurement result, which is read according to first-in, first-out (FIFO).

Fig. 8Full-screen View

(Color online) TDC design in the FPGA, including a 6-bit fine-time measurement and a 26-bit coarse counter measurement that constitute a final 32-bit time measurement result (with a 1.0737 s dynamic range and 333 ps bin size).

Figure 9 shows the tests that were conducted to confirm the functionality and performance of the FPGA-based TDC. The cable delay test method was used [13,14]. A signal source Tektronix AFG3252 (Beaverton, OR) generates two synchronized output signals (3.3 V CMOS level standard, 10 kHz repetition frequency), which are imported to two TDC channels in the FPGA [15]. By analyzing statistically the time interval of the two TDC channels’ output, the time resolution of a single channel can be obtained by dividing the RMS of the time interval by 2^1/2.

Fig. 9Full-screen View

TDC test platform setup based on the cable delay test method.

Figure 10 shows a typical histogram of time measurement results, with an RMS of 85 ps.

Fig. 10Full-screen View

(Color online) Normal curve fitting of the test data.

The RMS test results are given as follows: one test result is generated by circuit noise, and the second test results is produced by the quantization error. When the time interval between the two input signals in Fig. 9 changes, the RMS produced by the quantization error varies in a certain pattern, which is well described in Eq. (1) [16].

Where T_o is the bin size of the TDC, c is the remainder of T_o from time interval, and σ refers to the RMS result.

To accurately evaluate the TDC performance, we changed the time interval and conducted a series of tests (see the results inFig. 11). A characteristic relationship clearly can be observed, which agrees well with the expected results (marked with a dotted line in Fig. 11). A time resolution (RMS) no worse than 0.5 least significant bits (LSB) is obtained [17].

Fig. 11Full-screen View

(Color online) Eight-phase six-frequency doubling of 62.5 MHz FPGA-based TDC results, plotting the relationship between the RMS and the mean values of the time interval.

Characterization of the differential nonlinearity (DNL) and integral nonlinearity (INL) was performed based on the code density test method [18]. Code density is the number of times that every individual code has occurred. When the input signal is not correlated with the TDC clock, with a significant amount of data statistics, the count on each code corresponds to the bin width of that code, and then the DNL and INL can be calculated. Because each cycle has 48 bins of the CLK_SYS, the nonlinearity is periodic and corresponds to a repeating pattern of every 48 bins. Figure 12 shows the DNL and INL test results which indicate that the DNL and INL are both better than ± 0.2 LSB.

Fig. 12Full-screen View

(Color online) DNL and INL less than 333 ps FPGA-based TDC. The DNL is in the range of −0.2 to +0.15 LSB, whereas the INL is in the range of −0.15 to +0.15 LSB.

On the basis of this interpolation method, we successfully achieved a high resolution TDC with a bin size of 333 ps, which is beyond the application requirement. In addition, it has the advantage of low logic resource consumption (469 logic elements per channel) and a large dynamic range (1.074 s) compared with the systems listed in Table 2.

3.3. USB interface for data readout

A standard USB 2.0 interface is integrated in the test system to transfer the test data to a remote computer. As shown inFig. 13, a single-chip integrated USB 2.0 transceiver CY7C68013A (Cypress®; San Jose, CA) is used. In this work, the chip was programmed as 16-bit data interface, and end-point 2 (EP2) was programmed to transfer the command from a remote PC to the FPGA, and the EP6 was programmed to transfer the test data from the FPGA to a remote PC [19]. A FIFO (1024-word depth, 32-bit input width, and 16-bit output width) was integrated into the FPGA to communicate with the USB. To read out the data through this USB interface, we also designed test software based on Visual C++ (details are presented in Sec. 3.4), with an embedded USB driver.

Fig. 13Full-screen View

USB 2.0-based data acquisition. CY7C68013A is used to connect the FPGA and remote PC with a data rate of 240 Mbps.

3.4. Test software

Figure 14 shows the frame of the software, which contains three independent threads. The control thread sends commands to the FPGA in the digitization module, the status display thread monitors system status in real time, and the data interface thread stores the data to the hard disk.

Fig. 14Full-screen View

Software frame: three threads are running parallel to achieve data acquisition.

Figure 15 shows this software’s GUI (graphical user interface), which contains all necessary functionalities.

Fig. 15Full-screen View

Test system GUI.

4.1. Functionality test

The ASIC functionality test was conducted by observing the transient waveforms of the critical points of the ASIC using an oscilloscope, as shown in Fig. 17. These waveforms agree well with the ASIC simulation results, which indicate that the ASIC functions well.

Fig. 17Full-screen View

(Color online) Waveforms of the ASIC output signals. The reference and input signals are generated by the signal source (Tektronix AFG3252), and the T_out and Q_out signals are the output of the ASIC. The amplitude scale is 700 mV/div, 50 mV/div, 100 mV/div, and 100 mV/div from top-down.

In the test, the signal generator outputs two signals. One signal is created by the waveform of the PMT output signal, and it becomes the input signal (in Fig. 17) after passing through a 30-m cable. The second signal is a synchronization signal from the signal generator (i.e., the reference signal in Fig. 17), and a predetermined time interval exists between the input and reference signals. The signal T_out is the output of the ASIC discriminator, whereas the signal Q_out is the output of the QTC. By analyzing the time measurement results between the reference and T_out signal (i.e., the delay in Fig. 17), time measurement performance can be estimated; by analyzing the width of the Q_out signal, charge performance can be obtained.We then conducted a series of tests to evaluate the performance of the ASIC with this test system.

4.2. Time measurement result

The time performance test results of the ASIC are shown in Table 3 and Fig. 18.

Fig. 18Full-screen View

(Color online) Time measurement with the FPGA-based TDC; data are listed in Table 3.

As shown in Fig.18, the time walk (i.e. output signal delay of the discriminator compared with the input signal with different amplitudes) is around 10 ns, and the time resolution is more than 300 ps beyond the application requirement. The low V_th and high V_th refer to test results generated by the discriminator’s low (1/4 P.E.) and high (3 P.E. user-controlled) threshold (see Fig. 4). These two thresholds are employed to avoid deterioration of time measurement resolution, which would be caused by noise or interference in the baseline of the large input signal.

4.3. Charge measurement results

The charge information of the PMT signals (related to the amount of Cherenkov light) is converted to the width of a pulse signal in the QTC ASIC. By analyzing the digitization output of the FPGA-based TDC, charge measurement performance can be evaluated.

As shown in Fig 19, by combining the anode and dynode channel, a dynamic range of 1~ 4000 P.E. is covered, and the charge resolution is better than 10% RMS at 1 P.E. and 1% RMS at 4000 P.E., which are beyond the application requirements.

Fig. 19Full-screen View

(Color online) Charge measurement results with the FPGA-based TDC; data are listed in Table 4.

Using the test system presented in this paper, the ASIC chip designed for the WCDA in LHAASO was tested successfully and demonstrated performance sufficient for this application. With the modular structure of this test system and the design of a general-purpose digitization module, this test system can accommodate different ASIC versions that may be designed in future. In a bulk test of the final 3600 ASICs, multiple front-end modules will be designed, with sockets to mount the ASIC on the printed circuit board without soldering, and each digitization module can be used repeatedly.

4.4. Performance comparison

We also investigated the typical ASIC readouts for PMT with a large signal dynamic range, and list their performances in Table 5. Compared with these ASICs, the performance test results of our ASIC indicate a larger dynamic range with good time and charge measurement resolution.