A. DUTs

In this work, two kinds of SRAM devices were selected for azimuthal effects testing. The first kind is upset hardened by DICE [10], which is immune to single node charge collection and the sensitive node pairs must be simultaneously struck for an upset to occur [13]. The other kind is a military-level SRAM device from the Integrated Device Technology (IDT) company, which can be very sensitive to MBU [16-18] due to the layout of the memory cells. Details regarding the DUTs are reported in Table 1. The DICE SRAMs are in a thin quad flat package (TQFP) and the MBU-sensitive SRAMs are in a ceramic dual in-line package (DIP). All the test devices were de-lidded before heavy-ion exposure. IDT SRAMs contain a polyimide layer of about 60 μm on the top of the die, which was considered in the calculation of ion energy, range, and LET.

B. Radiation source

Heavy-ion irradiations were conducted at the Heavy Ion Research Facility in Lanzhou (HIRFL), using Argon (Ar), Krypton (Kr), and Bismuth (Bi) ions with an initial energy of 25, 25 and 9.5 MeV/u, respectively. Details regarding the beam characteristics under normal incidences are presented in Table 2. The ²⁰⁹Bi beam experiments were conducted in the vacuum chamber, while the ⁴⁰Ar and ⁸⁴Kr beam irradiations were performed in air with heavy-ions passing through a vacuum/air transition foil. A flux detector was placed in the beam line before the DUTs to monitor the real-time beam flux. The ion linear energy transfer (LET) in the DUTs was conveniently adjusted by either inserting energy degraders into the beam line (such as aluminum foils) or using angled ion strikes, i.e., the effective LET method [3]. For the angled ion strikes, the effective LET was increased by a factor of 1/cosθ, which can be expressed by the formula

where LET_eff is the effective LET of tilted ions incident at an angle of θ from the normal to the surface plane of the device and LET₀ is the initial ion LET at normal incidence.

The test boards were mounted on a four-dimension-movement platform, which allows for convenient device rotations. As shown in Fig. 1, the beam direction is defined by a tilt angle, θ, and azimuth, φ. Tilt angle controls the angle from the normal to surface plane of the device, i.e. from the positive Z-axis. Azimuth controls the angle from the projection of the incoming beam on the surface plane to the positive X-axis. The maximum tilt angle was performed under different azimuths, as long as the die would not be shadowed by the surrounding package material (which is not depicted in Fig. 1). The upset data was obtained and compared as the effective LET, i.e. the tilt angle of incident ions is the same. During the experiments, other factors, such as beam flux, temperature, preset patterns of test devices, mode of the test system, etc., are kept constant.

Fig. 1.Full-screen View

(Color online) Schematic diagram of the beam direction. For clarity, the DUT is represented by sensitive volumes covered by overlayers and the substrate is not depicted.

C. Test systems and MBU identification

Tests were performed in a dynamic mode with a checkerboard pattern input at room temperature. The memories were continuously scanned by a field programmable gate array (FPGA)-based tester. Once one bit-error was detected, several steps were performed automatically by the tester: (i) reading the erroneous bit again for confirmation; (ii) recording the bit-error information including error address, error data, and time interval of the previous error; (iii) correcting the erroneous bit; and (iv) reading the bit again to confirm the correction. The steps are finished in less than 2 μm (depending on the preset access time), then the scan process will continue at the next logical address. More than 100 bit-errors were accumulated under each test condition, in order to obtain good statistics. SEU cross sections were calculated by

where N_bit-error is the number of detected bit-errors, F is the beam fluence with a unit of ions/cm², and N_b denotes the device capacity. The device current was also monitored for protecting the devices burnout from a single event latchup (SEL). Once the current exceeds the preset threshold value, the power supply will be shut down automatically and the device will be reset.

For MBU identification, the recorded logical error addresses of bit-errors were converted to physical addresses based on the memory bit map [16]. One error cluster is treated as a MBU based on the following rules: (i) the errors are physically adjacent; (ii) the error data are the same due to the interleaving architecture of the test devices; and (iii) the time intervals are less than the loop period to make sure that the errors in the cluster were detected in the same loop. A few special cases, which could not be identified by those rules, were judged carefully during the identification process. Validity of those identification rules can be estimated as follows. The predominant failure mode is double adjacent bit-flips caused by two ions within the same scanning loop, whose probability can be calculated as follows:

where T_loop is the time of a scanning loop and R is the bit-error rate (errors/s) while irradiating, which can be controlled by the beam flux. For instance, with N_b = 262144 bits, a T_loop = 6.6 ms and R = 10 errors/s. Then, the failure probability equals 1.3×10^-7 per loop. In fact, for the ∼ 10000 bit-errors accumulated during the total SEU testing, there is only ∼ 2% of probability that an erroneous judgment happened. Low beam flux and high scanning speed are necessary to make the identification rules valid. The MBU patterns under different azimuths were also summarized for comparison.

A. SEU cross section

SEU cross sections of DICE-4Mb and DICE-8Mb SRAMs under normal and tilted incidence are shown in Fig. 2. Depending on the test devices, a discrepancy from 24.5% to 50% is shown between two perpendicular azimuths (A0 and A90) at the same tilt angle of 30 for ⁸⁴Kr ions. While the ²⁰⁹Bi ions with a tilt angle of 30 show no clear difference in the SEU cross section between two reverse azimuths (A0 and A180). The large decrement of SEU cross sections at a tilt angle of 45 and an azimuth of 180 is attributed to the shadowed die by the surrounding package material. As a consequence, only part of SVs in the memory were exposed to irradiation, which should be paid special attention to during angular measurement of device sensitivity.

Fig. 2.Full-screen View

(Color online) SEU cross sections of DICE-4 Mb and 8 Mb SRAM devices are plotted as a function of effective LET. The ⁸⁴Kr and ²⁰⁹Bi ions were used to irradiate the devices. Under tilt angle of 30 of ⁸⁴Kr ions, azimuths of 0 and 90 were performed and compared. Under tilt angles of 30 and 45 of ²⁰⁹Bi ions, azimuths of 0 and 180 were performed and compared.

Note that, at a LET value of 92.6 cm²/mg, the SEU cross section of DICE-4Mb SRAM under normal incidence equals 4.61×10^-5 cm²/device, i.e., 1.1×10^-11 cm²/bit (treated as the plateau cross section here), which corresponds to a surface area of SV in a memory cell of about 0.0011 μm² in the RPP model. This result can be very misleading during on-orbit error rate prediction of this RHBD-SRAM, which is built with 0.18 μm CMOS technology. If the depth of SV is routinely set as 1 μm (as in the CRÈME [6] or Space Radiation software [19]), this will create a long RPP with an inappropriate width(length)/depth ratio, resulting in an incorrect on-orbit error rate prediction. Moreover, the SEU cross section exhibits significant dependence on the tilt angle. The SEU cross section under a tilt angle of 60° for ⁸⁴Kr ions is more than one order of magnitude higher than that under normal incidence. Inverse-cosine law in the effective LET method [1] does not apply in this kind of design because the SEU cross section under a tilt incidence of 60° for ⁸⁴Kr ions (with an effective LET of about 75 cm²/mg) is one time larger than that under normal incidence for ²⁰⁹Bi ions (with an LET of about 92.6 cm²/mg). Additionally, the SEU cross section continues to increase quickly, even in the effective LET range of 92.6 to 131 cm²/mg. One time increment was observed as the tilt angle changed from 0° to 45°.

The underlying reasons for the azimuthal dependence or independence of SEU cross section on DICE-SRAM devices lie in the device layout. A simple schematic of the DICE structure is shown in Fig. 3. As mentioned previously, the DICE topology requires a charge collection at two sensitive volumes in a memory cell for an upset to occur. Thus, the main mechanism for triggering a SEU is charge sharing, which results from the diffusion process and parasitic bipolar conduction [20], given that the incident ion cannot directly strike the two sensitive nodes simultaneously. As a consequence, the average physical distance between the two sensitive volumes along different axes, which affects the preference of the diffusion process, is a key parameter in determining the SEU response under different azimuths. The inherent anisotropic layout of RHBD structures leads to the azimuthal dependence of SEU cross sections. Similarly, due to the symmetrical distribution of sensitive nodes along the X-axis, no azimuthal dependence was observed between the azimuths of 0° and 180°.

Fig. 3.Full-screen View

The DICE memory cell.

The SEU cross sections of IDT-256kb and IDT-64kb SRAMs under normal and tilted incidence are shown in Fig. 4. Three azimuths (A0°, A45° and A90°) at tilt angles of 30° and 45° for ⁸⁴Kr ions were performed, but no clear azimuthal dependence was observed for both IDT SRAM devices. The SEU cross section also exhibits weak dependence on the tilt angle. Those results are attributed to the fact that the SEU cross section tends to plateau in the LET region of ⁸⁴Kr ions and will be further discussed in the next section. Note that the SEU cross section in Fig. 4 is calculated by Eq. (2), which counts a MBU as several errors. If we count a MBU as one error, the plateau cross section of the IDT-256kb SRAM is about 1.6×10^-7 cm²/bit, corresponding to a surface area of SV in a memory cell of about 16 μm² in the RPP model. Unlike the DICE-SRAM discussed previously, this value fits with the reverse-engineering results shown in Fig. 5, which also supports the validity of our test results.

Fig. 4.Full-screen View

(Color online) The DICE memory cell. SEU cross sections of IDT-256kb and 64kb SRAM devices are plotted as a function of effective LET. The ⁴⁰Ar and ²⁰⁹Bi ions were used to irradiate the devices under normal incidence. Under tilt angles of 30° and 45° of ⁸⁴Kr ions, azimuths of 0°, 45° and 90° were performed and compared.

Fig. 5.Full-screen View

(Color online) Scanning Electron Microscope (SEM) picture at POLY of IDT-256kb SRAM device after reverse engineering. Two NMOS drains in the 4-transistor, polysilicon resistor load SRAM cell are marked in the figure. One of them is considered as the SEU sensitive region, depending on the storage state of the memory cell.

B. MBU ratios and patterns

For the DICE-SRAM devices, due to the hardened design, only a few DBUs were detected under the largest tilt angle. Thus, no enough data was acquired to investigate the azimuthal dependence on the MBU ratio. While for the IDT-256kb SRAM, as studied by Koga et al. [16] and our previous work [17, 18], MBU can be easily triggered under tilted incidence. Moreover, we found that under normal incidence, MBU accounted for more than half of all the bit-errors at an LET value of 37.4 cm²/mg, with increasing probability as tilt angle increased. However, the increment of MBU ratio as tilt angle changed from 0° to 45° was less than 10% and no clear difference was observed between MBU ratios under different azimuths and the same tilt angle, which explained the weak dependence of SEU cross sections on the tilt angle and azimuth (note that the SEU cross section here treated a MBU as several errors).

To analyze the MBU characteristics in more detail, MBU patterns under different azimuths are further investigated. Here, MBU pattern means the physical arrangement of the flipped-bits in a MBU. DBU patterns induced by ions at normal and tilted incidences under three azimuths are reported in Table 3. For the normally incident ions, the majority of DBU events involved two adjacent cells along the X-axis, followed by the occurrence of two adjacent cells along the Y-axis and two cells in the diagonal. The underlying reasons are discussed as follows. As shown in Fig. 5, sensitive regions of adjacent cells are periodically separated by the bitline/bitline bar (BL/BLB) contacts along the Y-axis direction, causing anisotropic distribution of sensitive volumes in the device layout. Thus, charges created by normally incident ions in the p-well can more easily diffuse to be shared by horizontally adjacent cells, due to the shorter inter-cell distance, leading to more DBUs along the X-axis.

TABLE 3.Full-screen View

Cumulative DBU patterns induced by ⁸⁴Kr ions at normal incidence and at tilt angle of 30° and 45° under three azimuths in IDT-256kb SRAMs

Tilt angle	Azimuth	DBU patterns
0°	0°	107	63	24	0	1
30°	0°	126	58	15	0	0
	45°	129	82	29	0	1
	90°	97	65	23	0	1
45°	0°	170	52	15	0	1
	45°	143	57	30	0	0
	90°	97	98	16	1	1

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For the tilted incidence, DBU patterns induced by ions under three azimuths are listed in Table 3. Here, we define a parameter, R, which equals the amount of along-X-axis DBUs divided by the amount of along-Y-axis DBUs, as a useful parameter for comparison. Note that R varies dramatically from 3.3 to 1 as the azimuth of incident ions changes from 0° to 90° (with tilt angle of 45°). Additionally, tilted ions at the diagonal incidence, i.e., under an azimuth of 45°, induce about twice the amount of diagonal DBUs than the other two azimuths with a tilt angle of either 30° or 45°. Those results suggest that tilted ion-induced MBU patterns are ion trajectory-oriented. As illustrated in Fig. 5, although the tilt angle is the same, the direction of ion trajectory among the SVs is different for beam with A0° or A90°, inducing preferable DBU patterns along the incident direction. To conclude, the beam direction relative to the layout of the device strongly impacts the DBU patterns, which are also affected by the spatial layout of SVs.

Due to smaller dimensions, compared to other patterns, L-shaped and square-shaped configurations are the predominant patterns of TBU and QBU, respectively (see Table 4 and Table 5), regardless of the beam direction. Similar results about predominant MBU patterns induced by protons with different energies were shown and discussed in Ref. [21]. Trajectory-oriented patterns are identified again in the non-predominant QBU patterns, although fewer events were observed.

TABLE 4.Full-screen View

Cumulative TBU patterns induced by ⁸⁴Kr ions at normal incidence and at tilt angle of 30° and 45° under three azimuths

Tilt angle	Azimuth	TBU patterns
						others
0°	0°	70	0	0	0	0
30°	0°	77	2	0	0	1
	45°	83	3	1	0	0
	90°	94	1	0	0	0
45°	0°	89	5	1	0	0
	45°	102	4	0	1	0
	90°	114	0	0	0	0

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TABLE 5.Full-screen View

Cumulative QBU patterns induced by ⁸⁴Kr ions at normal incidence and at tilt angle of 30° and 45° under three azimuths

Tilt angle	Azimuth	QBU patterns
							others
0°	0°	7	0	0	0	0	0
30°	0°	1	0	0	0	0	0
	45°	3	0	0	0	0	0
	90°	4	0	0	0	0	0
45°	0°	7	3	1	0	0	0
	45°	4	1	1	0	0	1
	90°	6	0	0	4	2	2

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