Heavy ion induced single event upset sensitivity evaluation of 3D integrated static random access memory

NUCLEAR ELECTRONICS AND INSTRUMENTATION

Heavy ion induced single event upset sensitivity evaluation of 3D integrated static random access memory

Xue-Bing Cao，

Li-Yi Xiao，

Ming-Xue Huo，

Tian-Qi Wang，

Shan-Shan Liu，

Chun-Hua Qi，

An-Long Li，

Jin-Xiang Wang

Nuclear Science and Techniques

Vol.29, No.3

Article number 31

Published in print 01 Mar 2018

Available online 19 Feb 2018

DOI：10.1007/s41365-018-0377-1

58700

Heavy ion induced single event upsets (SEUs) of static random access memory (SRAM), integrated with three-dimensional integrated circuit (3DIC) technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross-sections and multiple cell upset (MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions. In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers (LETs). The average percentage of MCUs of 3D SRAM increase from 17.2 to 32.95%, followed by the energy of ²⁰⁹Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-to-face structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross-sections of planar SRAM with experimental data. The upset cross-sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

3D integrationSingle event upset (SEU)Multiple cell upset (MCU)Monte Carlo simulation

I. Introduction

As a result of technology scaling, single event effects (SEEs) induced by the strike of high-energy particles have become a major challenge in modern nanoscale complementary metal-oxide-semiconductor integrated circuits (CMOS ICs). The single event upsets (SEUs) resulting from the incident particles induce storage state change in sequential logic circuits, remaining dominant in the 32-nm technology process [1]. In particular, in the declining critical charge and proximity of the transistors, a single particle can induce increasing multiple cell upsets (MCUs) as the deposited charges are collected by the adjacent SRAM cells. Different kinds of particles affect the reliable operation of ICs, for example, the α particle emitted from the radioactive impurities in package materials and neutrons or protons generated from high energy cosmic rays [2,3]. In the past, the negligible low energy proton and muon have been a major consideration in single event evaluations for more advanced technology [4,5]. Compared with other particles, heavy ions deposit more energy per unit depth along their tracks by directly localizing ionization or through indirect nuclear reactions. These ions are a vital single event source. Consequently, the evaluation of the sensitivity of heavy ions is required [6].

3DIC technology, as an alternative technology in avoiding the negative effects of the technology scale, has gained interest in the field of IC design and research. This technology has modified the traditional integration mode by stacking two or more layers of transistors vertically and horizontally [7]. By combining two or more IC wafers, the 3DIC technology enhances the density of transistors per unit area and the flexibility of placement and routing with the use of the through-silicon Vias (TSVs) technique. Moreover, the transportation delay time for the different logical units in various dies is shortened significantly by optimizing the IC layout. In addition, for a hybrid IC designer, this stack technology optimizes the design for a specific function or application, and electromagnetic interference can be reduced by placing both digital and analog modules in the different dies, enhancing the noise performance of the circuit systems.

The 3DIC technology has great potential for space and military applications due to the limitations of spacecraft volume and performance. Therefore, it is necessary to research the 3DIC vulnerability, as operated in a harsh environment. The sensitivity of planar SRAMs induced by heavy ions has been widely studied. Since 1997, Robert et al. analyzed the impact of individual ionizing heavy ions on SRAMs [8]. Damien et al. led an in-depth study on the multiple-bit upset (MBU) cross-sections of heavy ions for 90-nm SRAMs [9]. Boorboor et al. evaluated the impact of the radial dose effect on SEUs irradiated by heavy ions [10]. However, the SEE characteristics of 3DIC for various particles, especially the heavy ions, remain unclear. Pascale et al. reported the experimental results of 3×64 k 150-nm silicon-on-insulator (SOI) SRAMs. The proton irradiation and 14 MeV neutron irradiation results are discussed, indicating that the upset cross-sections for vertically integrated SRAMs are similar for all three dies. For the heavy ions, no results are presented [11]. Peng Li et al. performed research on the impact of heavy ion species and energy on the SEE characteristics of 3DIC. However, the relationship of the upset cross-sections with the LET and MCU phenomena are not included in this work [12].

In this study, the SEU sensitivity of the SRAMs that are 3D integrated into five dies, was identified. A nested sensitive volume model based on NCSU 45-nm PDK was calibrated using the TCAD tool. The 3D SRAM simulation model with five dies was developed in Geant4. The heavy ions of the different species and energies were simulated. This research had the following findings. First, no obvious die-to-die effects were observed for the 3D SRAM when LET had an excess of 15.63 MeV·cm²/mg, and the upset cross-sections of 3D SRAM showed a noticeable discrepancy at low LET. Second, the MCU percentage of 3D SRAM increased with decreasing energy of the incident ²⁰⁹Bi for the considered energy range. A significant difference in the MCU percentage was observed for back-to-face and face-to-face structures. Third, the comparisons of the cross-sections of the planar SRAM, 3D SRAM, and experimental data are presented. The results indicate that the vulnerability of 3D SRAM is similar to that of the planar process, and the 3DIC technology is applicable to the aerospace and military fields.

II. Extraction of Sensitive Volumes

The basic structure of an SRAM cell is shown in Fig.1. Usually, every SRAM cell has two sensitive transistors with its storage state for Q=0, QN=1 or Q=1, QN=0 (Fig.1). For example, when Q=1 and QN=0, P1 and N2 are conducted; whereas, P2 and N1 are cut off. If an ion strikes the drain region of P2, the off-transistors begin to collect charges due to ions that strike through the space-charge region located in a reverse-biased p-n junction. If the deposited charges exceed the critical charge, the P2 transistor will be conducted, forcing the storage state of the SRAM to change to Q=0, QN=1, and an SEU will be produced. If the generated charges are collected by the sensitive transistors of the adjacent SRAM cells, the storage state of those SRAMs may all be changed, which refers to the MCUs.

Fig.1.

Basic structure of 6-TSRAM cell, P2 and N1 become sensitive transistors when Q=1 and QN=0.

A. Calibration of sensitive transistors

To analyze the affected regions due to ionization caused by ions striking the sensitive transistors of a SRAM, the TCAD models were initially calibrated on NCSU FreePDK3D45 v1.1. The width and length of P1 and P2 were 70-nm and 55-nm while the width and length of N1 and N2 were 240-nm and 55-nm, respectively. In addition, the doping concentration of the P-substrate, and the drain and source were 1×10¹⁶ and 2×10²⁰ cm^-3, respectively. The size of the P-substrate in the TCAD simulation was 10 μm×10 μm×10 μm. The physical models used in all of the TCAD simulations included: (1) Fermi-Dirac statistics, (2) band-gap narrowing, (3) Shockley–Read–Hall (SRH) recombination and Auger recombination, (4) doping, electric field, carrier-carrier scattering, and interface scattering effects on mobility, and (5) a hydrodynamic model used for carrier transport [13]. The electrical characteristics of both the PDK and TCAD models were matched and the curves of both the TCAD and SPICE are shown in Figs. 2 and 3.

Fig.2.

I_drain - V_drain current curves of the SPICE and TCAD models for (a) NMOS and (b) PMOS.

Fig.3.

I_drain - V_gate current curves of the SPICE and TCAD models for a NMOS, b PMOS.

B. Partition of sensitive volumes

Generally, the classic rectangular parallelepiped (RPP) model is utilized to simulate the sensitive regions of a transistor. However, the accuracy of RPP model, which is used to estimate the cross-sections of more advanced SRAMs, has been questioned due to the technology scaling [14]. In this work, a nested sensitive volume model was calibrated. The size and position were taken from a combination of TCAD and SPICE simulations. During the simulations, the sensitive transistors were built by TCAD using the calibration results in II A, and the extra transistors adopted in the SPICE models. Heavy ions with LET=5, 10, and 15 MeV·cm²/mg strike the center of the drain region of the off-NMOS and off-PMOS. The heavy ion strikes were modeled as a Gaussian distribution along the striking path. The charge track radius and length were 50-nm and 10-μm, respectively, and the ion strikes occurred at 1 ns. The particle incident position increased at a step of 0.02-μm from the center of the drain to 0.2-μm, and increased at the step of 0.05-μm to 0.5-μm. Fig.4 shows the collected charges at the different incident positions from the center of the drain for the NMOS and PMOS transistors. The sensitivity of the turn-off transistor presented an obvious change within 0.2-μm, compared with the region beyond 0.2-μm, where the amount of the collected charges decreased slightly. This implied that the collected charges by the drain in this region had little influence on the sensitivity of the transistor. Accordingly, the nested sensitive volumes (SVs) were limited in the range of 0.2-μm from the center of the drain for the sensitive transistors in the SRAM cells.

Fig.4.

(Color online) Collected charges of sensitive transistors versus incident position, for (a) NMOS and (b) PMOS.

The depth of the SVs is estimated as follows:

L_{i} = Q_{i, collected} / L E T,

(1)

where $Q_{i, collected}$ is the amount of collected charges in the ith SV and LET is a parameter of the incident ion. The energy loss per unit length when ions pass through the material, in the standard units of Mev·cm²/mg, can be expressed in Pico coulomb per unit (pC/μm) by multiplying by 100 [15].

The collection coefficient $α_{i}$ of each SV can be calculated as follows:

α_{i} = Q_{collect_svi} / Q_{collect_drain},

(2)

where, $Q_{collect_drain}$ is the charges collected by the drain when ions strike the center of the drain region, $Q_{collect_svi}$ is the average charge collected by the ith SV. Five SVs of off-PMOS and off-NMOS for a SRAM cell were built using this process.

III. Monte Carlo Simulation

A. Construction of the simulation model for 3D SRAMs

The 3D SRAM model for the Monte Carlo simulations is indicated in Fig.5(a). It was a refined model, designed by referencing the NCSU Free PDK3D45 design kit [16]. The 3D SRAMs simulation model consisted of five dies, and each die included 16×16 SRAM cells. The nested five SVs of PMOS and NMOS were located on the substrate of each die. The structure sizes of all the SVs were calibrated using the TCAD simulations in Sec. 2. In the 3D simulation model, the first wafer was bonded to the face-to-face structure, and the other wafers were designed using back-to-face bonding. Figs. 5(b) and 5(c) schematically depict a two-layer stack assembled in the back-to-face and face-to-face structures, respectively. The back-to-face structure was based on bonding the front side of the bottom die with the back side of the top die. The face-to-face structure was achieved by joining the front sides of two wafers. The advantage of the face-to-face structure is the ability to attain much higher interconnect densities by decoupling the number of TSVs from the total number of interconnections between the layers. Consequently, the face-to-face structure reduced the process complexity compared to the back-to-face structure. Each die of the simulation model had 10 metal routing layers and one top metal layer, as shown in Fig. 5(d). The dies B to E had additional back metal layers, used to connect the different dies. A tungsten layer was also added to the metal layers to simulate the connection between metals. The total thickness of the structure was 284.3 µm.

Fig.5.

(Color online) (a) Simulation model of 3D SRAM (not all SVs are illustrated in this figure due to page limitations), (b) and (c) are the back-to-face and face-to-face structures, and (d) is the layer information of a single die in the simulation model.

B. Physics Process and Heavy Ion Sources

In this work, for the Monte Carlo simulations we utilized a program package based on Geant4 which is a complete simulation toolkit for the emulation of the passage of particles through matter [17]. To simulate the actual physical process between incident ions and the device using the Monte Carlo simulations, ionization, nuclear elastic, and inelastic reactions, including screened Coulomb scattering were considered as the physical processes [18]. For example, the G4EmStandardPhysics class can accurately simulate the electro-magnetic processes and was adopted in the physics list. G4ionIonisation and G4hIonisation were used to simulate the continuous energy loss due to ionization and delta rays produced by charged ions. G4HadronElasticeProcess and G4HadronInelasticProcess were used to simulate the process of nuclear reactions. G4ScreenedNuclearRecoil were used for sensitive volumes to calculate the non-ionizing energy loss during atomic motion. G4hMultipleScattering were adopted to simulate the elastic scattering of charged particles and electrons.

The heavy ion species and energies were referred from the Brookhaven National Laboratory (BNL) and Heavy Ions Research Facility in Lanzhou (HIRFL). High-energy ions were adopted in the simulations by considering their range and the focus of this work was to investigate the different sensitivities for each die in the 3DIC. The parameters of the adopted heavy ion beams, including ion species, their associated energies, effective LET, and stopping ranges in silicon are showed in Table 1. All parameters were generated using SRIM2013 [19]. During each Geant4 simulation, there were 10⁵ mono-energetic ions randomly striking the surface of the 3D SRAM model at normal incidence for each ion type and energy.

Heavy ion irradiation parameters in silicon used in Monte Carlo simulations

Ions	Energy(MeV/u)	Effective LET(MeV·cm²·mg^-1)	Range(μm)
³⁹Ar	96.15	2.051	4570
	35.90	4.269	867.28
	16.67	7.208	260.16
¹³²Xe	106.06	15.63	2390
	68.18	20.95	1190
	34.09	32.62	423.34
²⁰⁹Bi	71.77	42.19	1080
	38.28	58.57	464.63

C. SEUs calculation process

Fig.6 shows the calculation process of the SEU cross-sections of each die. An incident ion was projected from particle gun, striking the surface of the simulation model. The collected total energy in the SVs is calculated as:

Fig.6.

SEUs calculation process in the Monte Carlo simulations.

E_{Sens,NMOS} = \sum_{i = 1}^{N} α_{i} E_{{SV}_{i}, NMOS}

(3)

E_{Sens,PMOS} = \sum_{i = 1}^{N} α_{i} E_{{SV}_{i}, PMOS},

(4)

where N is the number of nested SVs, and $E_{S V_{i, NMOS}}$ and $E_{S V_{i, PMOS}}$ are the collected energies of ith SV for the NMOS and PMOS transistors, respectively. $E_{S e n s, N M O S}$ and $E_{S e n s, P M O S}$ are the total collected energies for the sensitive NMOS and PMOS, respectively, during an ion strike. The deposited energy of the sensitive transistors in each SRAM cell due to the interaction between the ions and devices was converted to charges using Eqs. (5) and (6), and $Q_{c o l l e c t e d, N M O S}$ and $Q_{c o l l e c t e d, P M O S}$ are the collected charges for NMOS and PMOS, recorded to ROOT for the integrated counts, respectively.

Q_{collected,NMOS} = (1 / 22.5 MeV) \times E_{Sens,NMOS}

(5)

Q_{collected,PMOS} = (1 / 22.5 MeV) \times E_{Sens,PMOS}

(6)

The critical charge (Q_crit) is defined as the minimum charge to generate one bit of upset for a SRAM cell. Usually, the device structure, doping concentration, and reverse bias voltage are used to measure the critical charge. The critical charge used in this work was obtained by combining the SPICE and TCAD simulations. The sensitive transistor models of the SRAM cell were built using the TCAD tool. The LET of ions striking the center of the drain of the sensitive transistors gradually increased until a node state was changed from 0 to 1 for NMOS, or from 1 to 0 for PMOS. The LET that caused the storage state to change was considered as the threshold LET and the charge quantity collected by the drain of the sensitive transistor was the critical charge. In this work, when the LET of the incident ions striking NMOS reached 0.26 MeV·cm²/mg, the storage state began to change. The collected charge quantity was 1.5 fC while in the same process of the PMOS transistor, the critical charge was ~ 4.2 fC.

When the collected charges resulting from the deposited energy exceed the critical charge, an SEU is induced, as described by Eqs. (7) and (8). A SEU event may include single bit or multiple cell upsets. The ith incident ion is denoted by n_i. If the ith incident ion penetrates the SVs (the SRAM cell shown in Fig. 1) at a certain working state, such as Q = 1 and QN = 0, and the collected charges in the sensitive transistor NMOS1 or PMOS2 of the cell exceed $Q_{c r i t, P M O S}$ or $Q_{c r i t, N M O S}$ , a one-bit flip should be induced. In this work, the proportion of the storage state in node Q is the same for 0 and 1 to simplify the analysis process. After every particle event, all SVs in each die were performed in this procedure. The number of SEUs and MCUs were counted in this process.

n_{i} = {\begin{matrix} 0 \\ 1 \end{matrix} \begin{matrix} \begin{matrix}  \end{matrix} \end{matrix} \begin{matrix} Q_{collected,NMOS2} < Q_{crit,NMOS} & Q_{collected,PMOS1} < Q_{crit,PMOS} (i = 1, \dots, N), \\ Q_{collected,NMOS2} \geq Q_{crit,NMOS} | | Q_{collected,PMOS1} \geq Q_{crit,PMOS} (i = 1, \dots, N) \end{matrix} for state 0

(7)

n_{i} = {\begin{matrix} 0 \\ 1 \end{matrix} \begin{matrix} \begin{matrix}  \end{matrix} \end{matrix} \begin{matrix} Q_{collected,NMOS1} < Q_{crit,NMOS} & Q_{collected,PMOS2} < Q_{crit,PMOS} (i = 1, \dots, N), \\ Q_{collected,NMOS1} \geq Q_{crit,NMOS} | | Q_{collected,PMOS2} \geq Q_{crit,PMOS} (i = 1, \dots, N) \end{matrix} for state 1

(8)

Consequently, the SEU cross-sections for each die are given by

σ_{tierj} (Q_{crit}) = \sum_{i = 1}^{N} n_{i} / (F \times N_{b} \times \cos (θ)),

(9)

where $F$ is the beam fluence with the unit of ions/cm², $N_{b}$ is the device capacity, and $θ$ represents the incident angle from the normal to the surface plane of the device. $θ$ =0 in our work due to the normally incident ions.

IV. Simulation results and discussion

A. Heavy ion upset cross-sections

The upset cross-sections of the five dies for 3D SRAM are presented in Fig.7, and there was a difference in the upset cross-sections of the five dies at low LET, of two orders of magnitude at LET=4.269 MeV·cm²/mg. The maximum difference rose to four orders of magnitude when the LET decreased to 2.051 MeV·cm²/mg. When the heavy ion LET reached 15.63 MeV·cm²/mg, the difference was essentially negligible for high LET from die B to die E. However, die A showed a smaller upset cross-section compared with the other dies.

Fig.7.

(Color online) SEU cross-sections versus LET for 3D SRAMs, the dies A to E represent the upset cross-sections of each die of the 3D SRAMs.

To explain this phenomenon, Fig.8 shows the relationship of the integrated counts versus the deposited charge for ³⁹Ar (LET=4.269 MeV·cm²/mg) and ¹³²Xe (LET=20.95 MeV·cm²/mg), respectively. When the LET was 4.269 MeV·cm²/mg, the high-energy tails of the integrated counts in Fig.8 (a) presented significant discrepancies. The sensitivity of each die showed an obvious difference at low LET. When the LET reached 20.95 MeV·cm²/mg, the high-energy tails of the integrated counts converged. The sensitivity of each die for 3D SRAM tended to be similar. The cross-sections of each die became increasingly similar. However, the curve of the integrated counts of die A shifted to the left, indicating that the sensitivity of die A decreased compared with the other dies. This also explains the trend of the upset cross-section of die A.

Fig.8.

(Color online) Integrated counts spectrum of deposited charge for the (a) ³⁹Ar (4.269 MeV•cm²/mg) and (b) ¹³²Xe (20.95 MeV•cm²/mg).

B. MCUs

Fig.9 shows the SBU and MCU percentages of ²⁰⁹Bi with energies of 71.77 MeV/u and 38.28 MeV/u. The simulation results showed two noticeable phenomena. The average percentage of the MCU of the five dies increased from 17.2 to 32.95% when the incident ion energy decreased from 71.77 to 38.28 MeV/u, and the proportion almost doubled. The occurrence of MCU was caused by the scattering effects of ions, secondary particles generated in nuclear reactions, and delta electrons produced during ionization. Under the comprehensive influences of those physical processes, the track of incident ions changed significantly and the energy density distribution around the track also became denser. In our simulations, the low speed of the ions with low energy increased the interaction time and scattering range. The dense column of the energy distribution acted more on the wide SVs and induced the energy collection of the surrounding SVs around the track of incident ions, producing the MCUs. To evaluate the effect of the ion track structure on the MCUs, a cylindrical block of silicon was built consisting of 10,000 cylindrical shells, with a thickness and height of 1 nm and 1 µm, respectively. The ion beam strikes the center of the cylinder during the simulations. The deposited energy in each shell was recorded. The geometric structure for simulating the radial dose distribution is shown in Fig.10. Fig.11 illustrates the radial distribution of the energy density around the track of incident ²⁰⁹Bi with energies of 71.77 and 38.28 MeV/u. Based on literature and previous reports of [20] and [21], the average affected area of SRAM for 45-nm technology is ~200 nm. The simulated results of the radial dose distribution for ²⁰⁹Bi indicate that the lower energy heavy ions produced greater energy density around the incident ion track within the sensitive area. The increased energy density made it easier to collect the energy for the SVs, increasing the ratio of MCUs accordingly.

Fig.9.

(Color online) Percentages of SBUs and MCUs of five dies for 3D SRAM for different energies of ²⁰⁹Bi.

Fig.10.

Geometric structure to simulate the radial dose distribution.

Fig.11.

(Color online) Radial distribution of energy density around the path of incident ions in silicon.

The simulation results also indicate that there are major differences in the percentages of SBU and MCU for face-to-face and back-to-face structures. For ²⁰⁹Bi with an energy of 38.28 MeV/u, the average percentage of MCUs in the back-to-face structure was 37.3% while in the face-to-face structure the ratio was only 5.54%. For dies B to E, which were bonded by back-to-face structures, the percentage of MCUs increased significantly for a deeper die. The MCUs ratio of die B was 51.76% compared with 24.73% for die E. Die B had the highest ratio of MCUs due to scattering effects and that the quantity of collected charges of ²⁰⁹Bi in die B was stronger than the other dies. The incident ²⁰⁹Bi had a stronger scattering ability in the high-Z material. Fig.12 shows the scattering scope of ²⁰⁹Bi during the simulations. The incident heavy ions were easier to scatter in the high-Z material and the ²⁰⁹Bi had passed through three layers of tungsten when they arrived at die B, inducing the scattering of ²⁰⁹Bi in die B. When the ²⁰⁹Bi strikes the tungsten layer, the elastic collision changes the motion direction, as shown in Fig.13. The track distance of ²⁰⁹Bi in the transistor layer was stretched due to the decreasing angle of the track and plane of the layer, so that the energy was deposited in a wider range of the die B transistor layers. The rising collected energy of the SVs in die B led to the increased ratio of MCUs of die B compared with the dies C to E. For die A, Fig.14 shows the integrated counts spectrum of the deposited charge for ²⁰⁹Bi at the energy of 38.28 MeV/u. The deposited energy in die A decreased, compared with the other dies. In spite of the scattering effect being the strongest in die A, the deposited energy decreased so much that the collected charges by adjacent SVs hardly exceeded the critical charge, which explains why the ratio of the MCUs in die A were less than that in die B.

Fig.12.

(Color online) Track of ²⁰⁹Bi at 38.28 MeV/u in 3D SRAM simulations.

Fig.13.

(Color online) Illustration of the track of the incident heavy ion in simulation model.

Fig.14.

(Color online) Integrated counts spectrum of deposited charge for ²⁰⁹Bi at 38.28 MeV/u.

C. Comparison of planar and 3D SRAM

To evaluate the different sensitivities of the integrated SRAM with the planar process and 3D technology, a simulation model of the planar SRAM was created. The planar SRAM structure was constructed by removing the interlayer dielectric isolation, metal interconnect layer, and substrate from dies B to E in the 3D structure as shown in Fig.5(a). As cited in the Monte Carlo process of the SEU calculation during the 3D SRAM simulations, these were used in the planar SRAM simulations. The upset cross-sections of both the planar process and radiation measurements, as a function of LET, are shown in Fig.15(a). The experimental data were from the literature [22], with the heavy ions measurement results of SRAM processed with 45-nm bulk technology. The comparison results indicated that there was no significant difference between the upset cross-sections of the planar process and experimental data for some cases. By considering the introduced errors due to the stochastic process in the Monte Carlo simulations, the experimental results dropped within the fluctuation of the simulation results. This proved that the simulation results of the planar SRAMs were mostly consistent with the experimental results. Fig.15(b) shows the comparison results of the upset cross-sections of planar and 3D SRAM. The results demonstrated the same sensitivity of the planar process and the 3D integrated process for high LET. For low LET, the upset cross-sections of planar SRAM were consistent with those of die A. The results indicated that the vulnerability of the 3D integrated process is not worse than that of the planar process.

Fig.15.

(Color online) SEU cross-sections versus LET for (a) planar process and experimental data, and (b) planar process and 3D technology.

V. Conclusion

Heavy ion induced single event effects have been evaluated extensively for planar technology. However, studies involving the impact of heavy ions on 3DIC technology are insufficient. It is useful to evaluate the sensitivity of 3DIC owing to its potential application in the aerospace and military fields. In this paper, the heavy ion induced single event and multiple cell upsets of 3D SRAM were analyzed. The SEU cross-sections for heavy ions with different species, energies, and LETs were simulated using the Monte Carlo method. The simulation results showed that the upset cross-sections of 3D SRAM were approximate for each die in high LET, but noticeable differences were observed in low LET. The percentage of MCUs also exhibited different trends in the face-to-face and back-to-face structures. The comparison of the simulation results of 3D SRAM with planar SRAM showed that the sensitivity of 3D SRAM was similar to that of the planar SRAM. The 3DIC technology is expected to have a vital application in the aerospace and military fields. However, further attention is required for the investigation of the sensitivity of 3DIC by considering the differences in the upset cross-sections in low LET. Additionally, the distinctions of the MCU sensitivity of the 3D SRAM with face-to-face and back-to-face structures should be evaluated in further research.

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