2.1 System structure

Figure 2 shows the architecture of ADAS [11]. It consists of four data acquisition plugins, one VXI crate with its controller, and one host computer. The plugins are responsible for data acquisition and processing. Each plugin has eight acquisition channels that offer 8-bit 1 Gsps sampling. The VXI crate provides sufficient space and power supply for over 32 channels. The host computer is responsible for controlling, data receiving and displaying for the entire system, and an IEEE 1394 cable is applied to transmit data between the VXI crate and the host computer.

Fig. 2Full-screen View

Architecture of the ADAS.

2.2 Hardware design

The VXI-based instrument is primarily in charge of signal acquisition and processing [12]. Fig. 3 shows architecture of the plugin. It consists of eight analog-front-ends (AFEs), four analog-to-digital converters (ADCs), two field-programmable gate arrays (FPGAs), the power supply unit, and a clock generator. The function of the VXI bus is to transmit data from the plugin to the host.

Fig. 3Full-screen View

Architecture of the plugin

The AFE focuses on receiving and conditioning the input signals [13]. Since the detectors are located in high-frequency electromagnetic interference (EMI) environment, a five-step LC anti-alias filter (AAF) is needed in front of the ADC. It can block high-frequency noise and limit the pass band at DC-125 MHz to increase signal-to-noise ratio (SNR).

Signals from Dragon-I detectors are of variable dynamic ranges, so the AFE gain should be adjustable to match dynamic range of the ADC input. Based on resistance adjustment, traditional method of gain control fails to meet the requirements of high integration and automation, and a fixed-gain amplifier cooperating with a digital step attenuator (DSA) is used for digital control. The gain parameters can be adjusted by regulating attenuation ratio of the DSA through VXI bus. Taking advantage of the high performance DSA, the AFE gain ranges from −21.5 dB to +10 dB in 0.25 dB steps.

Calibration of the AFE is always necessary, since the AFE would introduce gain error and DC offset, hence the decrease of accuracy. Automatic AFE calibration based on FPGA and ADC is used, rather than traditional manual calibration. As the input bias and the ADC gain are adjustable, the AFE input is first connected to the ground so that the AFE input bias can be removed through adjusting the ADC input bias. Next, a stable reference voltage is used as the AFE input and by regulating the ADC gain, and the AFE gain can be modified. The self-calibration process carries on automatically right after the system is powered on. Meanwhile, manual recalibration is available if necessary.

As function core of the VXI plugin, the two FPGAs are responsible for data receiving and processing, and control of slave devices as well [14, 15]. Fig. 4 shows the architecture of inner logic of the FPGAs. The serializer/deserializer (serdes) and data acquisition units receive data from the ADCs, while the data processing unit accomplishes signal analysis. Other units are responsible for system communication, coordinated control, and operation support.

Fig. 4Full-screen View

Architecture of FPGA logic.

2.3 Data acquisition and processing

To achieve high SNR sampling, a clock with extremely low aperture jitter (t_j) is needed. Eq.(9) is the definition of SNR [16].

As the jitter of sampling clock of this system must be less than 5 ps, the clock chip of LMK04821 is adopted to provide a 1 GHz synchronous sampling clock for ADCs with clock output jitter less than 300 fs.

ADC08D1000, an 8-bit 1 Gsps ADC is used for analog signal sampling. It has a 1: 2 demultiplexer that deserializes the 8-bit 1 GHz data stream into a 16-bit 500 MHz data stream, exporting the data stream via a low-voltage differential signaling (LVDS) bus. In the FPGA, the serdes unit deserializes the 16-bit 500 MHz high-speed data stream into 64-bit 125 Mbps low-speed data stream, which is then written into ring storage, where a section of the latest data can be captured and stored when triggered. Next, the processing module performs real-time analysis to obtain characteristic parameters of the signals, including amplitude peak, pulse width, rising and falling time, and average voltage of a specified region. Finally, the plugins upload both the raw data and the analysis results to the host.

The ADAS is located considerably far away from the detector, connected by tens or hundreds of meters of coaxial cables, making signal distortion a common issue during high-speed pulse transmission. Therefore, digital compensation in FPGA achieves raw signal reconstruction.

In general, skin effects of cables under high frequency causes signal attenuation and the insulating medium causes high-frequency loss, as described in Eqs. (10) and (11), respectively, where f is signal frequency, E and F are coefficients determined by the cable material and structure, d is the diameter of the conductor, ε is the relative dielectric constant, D is the insulation diameter, and δ is the dielectric loss angle [17].

Considering the influence of DC resistance, the attenuation expression a(f) can be simplified as Eq. (12).

Eq. (12) indicates the relationship between signal frequency and signal attenuation ratio through cables. With a digital sweeper, the frequency spectrum of the signals through each coaxial cable can be measured, and the coefficients of A, B and C can be calculated using least square method (LSM). When capturing the valid signal, the data processing unit obtains its discrete frequency spectrum using fast Fourier transform (FFT), and then modifies the spectrum using Eq. (12). Finally, the unit reconstructs raw signal through the inverse fast Fourier transform.

2.4 Realization of the trigger unit

The trigger unit determines the initial time of signal acquisition, playing a key role in data alignment. As the external trigger signal arrives randomly, a 16 ns jitter can occur between any two channels since the inner clock of the FPGA is up to 125 MHz. To reduce jitter between channels, high accuracy trigger position should be determined.

For this purpose, two time-to-digital converters (TDCs) [18-21] are used to obtain time measuring capability using the FPGA’s logic resources. As excessively short measuring time leads to low accuracy, the TDC measures the time interval between rising edges of the trigger and the next third rising edges of data clock (DCLK) to locate trigger position. However, the TDC will miss recording the rising edges if the time interval between the rising edges of the trigger and the nearest DCLK is less than 110 ps, leading to inaccurate calculation. Therefore, once receiving a trigger, the FPGA shall produce a 1250 ps delayed signal called Trigger_d through the IO delay primitive. The correct measured time is then calculated by analyzing the results of the measurements, t and t_d, as illustrated in Fig. 5.

Fig. 5Full-screen View

Diagram illustrating triggered time measurements t and t_d.

There are three cases worth considering, each of which is described below.

(1) If t−t_d is approximately 1250 ps, neither of the TDCs miss recording a rising edge; t is the measured time T.

(2) If t−t_d is approximately −2750 ps, TDC_A does not miss recording a rising edge; t is the measured time T.

(3) If t−t_d is approximately 5250 ps, TDC_B does not miss recording a rising edge; t_d +1250 ps is the measured time T.

Suppose the ADC sampling rate is 1 Gsps, the ADC’s output data are highly synchronous with the DCLK. Thus, suppose that the pre-trigger number is N, the calculated trigger position is (N+12−T) ns. When a plugin receives a trigger signal, it simultaneously broadcasts the signal to the rest of the plugins via the VXI backplane with an emitter-coupled logic (ECL) signal. Since the broadcast signal and clock synchronization pulse use the same transmission path, the time delay caused by different transmission distances cancels each other out. Through this method, the trigger position in the dataflow of every plugin is definite, thus realizing high-accuracy trigger across plugins.

2.5 Software design

The software is in charge of system initialization, data receiving and waveform displaying. Fig. 6 is its workflow. In system initialization, the software sends operation parameters according to the detector’s type and working conditions. It also specifies a plugin that is responsible for external trigger signal receiving. Next, the software commands the specific plugin to send a clock synchronization pulse via the ECL line to synchronize other plugins. On receiving an interrupt, the system reads data from the plugin and stores them on the computer’s hard drive. The host displays the signal waveforms on the monitor. In addition, the software provides an API for other programs to obtain data for further processing.

Fig. 6Full-screen View

Software workflow of our system

3.1 System performance test

For bandwidth test, we used a Fluke 9500B oscilloscope calibration workstation to generate fixed-amplitude sine waves with variable frequencies as input signal. Results showed the bandwidth of the 32 channels ranging from 117 to 132 MHz.

For gain error test, we used an AFG3102C arbitrary function generator to generate linear sweep signal V_s (−4.75 to +4.75 V, 100 kHz). Then the plugin measured the voltage and calculated the gain error by linear fit the measured data. The results indicated that the maximum gain error of each channel was less than 0.75%.

For ENOB performance test, we generated three sine waves of different frequencies using the Fluke 9500B as analog inputs (9.971 MHz with a 20-MHz low-pass filter, 59.971 MHz with a 100-MHz low-pass filter, and 99.971 MHz with a 200-MHz low-pass filter separately; 9.5 V in amplitude). The ADAS sampled the analog signals and calculated the ENOB. Test results showed that ENOB was always greater than 7.05 bits under the three conditions.

Finally, to test accuracy of the trigger, we used a pulse signal synchronized with the DCLK as trigger input, with repetitive measurement over 1000 times. Test results showed that the RMS accuracy of the trigger was 107 ps.

3.2 Field test

We operated the ADAS on the Dragon-I monitor system. Fig. 7 shows the reconstruction effect report. The power splitter divided the detector output into two signals: the green one, which was sent to the ADAS through a short cable; and the red one, which was transmitted through an 85 m cable; with its reconstructed waveform being shown in blue. Analysis results showed great consistency between the reconstructed signal and the original one, with flat-topped average amplitude error of <1.6% and pulse width error of < 2 ns.

Fig. 7Full-screen View

Results of the waveform reconstruction test

Fig. 8 is a screenshot of the ADAS software during the field test, reflecting the V-t transients of eight types of detected signals with a time base of 50 ns. Among all of the sampled signals, the fastest signal rising edge was 7 ns (see the enlarged section), suggesting that the system is competent in precise signal acquisition with a signal rising edge less than 10 ns.

Fig. 8Full-screen View

The ADAS-detected signals in the field test on Dragon-I.