1 Introduction

CYCIAE-100 [1-6] is an AVF cyclotron, which provides continuously adjustable energy (75 ∼ 100 MeV) and a high intensity (200 ∼ 500 μA) proton beam. The RF system of the CYCIAE-100 cyclotron consists of two half-wave cavities [7], two 100 kW RF amplifiers [8], and two sets of LLRF control systems [9, 10]. The two cavities are installed in the two opposite valleys and driven by two RF amplifiers [11] independently. It is different from the cavity of the CYCIAE-10 [12-16] cyclotron in that the two cavities are independent from each other. Thus, a phase close-loop control has to be used to make sure the two cavities are in phase [17].

The LLRF system of the CYCIAE-100 cyclotron is a flexible and modular system. It consists of six modules, which are 1: amplitude-control board; 2: tuning-control board; 3: signal-control board; 4: clock reference board; 5: beam buncher RF signal control board; 6: remote control board. It can be used to control a RF system of a single cavity cyclotron like CYCIAE-14 with module 1, 2, 3, and 6. It also can be used to control RF systems of multi-cavities cyclotron like the CYCIAE-100 or the CYCIAE-800(in the future) with module 1, 2, 3, 4, and 6. Figure 1 shows the RF system of the CYCIAE-100 cyclotron. The clock reference board provides a clock source and four phase-reference RF signals for the RF system. The two signal-control boards, which are comprised of a phase detector and a phase shifter(AD9954), share the clock source and two phase-reference signals and drive the two cavities independently.

Figure 1:Full-screen View

(Color online) The RF system of CYCIAE-100 cyclotron.

2 Phase control strategy

Rather than use one RF signal source and split it into two phase-referenced signal for the two LLRF system, the LLRF system of the CYCIAE-100 cyclotron uses three DDSs to control the phase of the two cavities. One of them is served as the traditional signal source, the other two DDSs are unique in their LLRF system design. This structure makes it easy to modulate amplitude and phase of the RF system. The frequency of the three DDSs are fixed to 44.8125 MHz for the CYCIAE-100 cyclotron. The amplitude of which is controlled for the start up logic, which uses a low power to protect the equipments when the system is power on. The phase of which is controlled for fast beam modulation [10]. The two cavities are psychically independent, thus the spark and recover procedure in one cavities will not affect the other cavities. In this point of view, this independent driven method gives a better availability over the hard connected cavities solution. However, one issue needed to be addressed before this RF system be put into daily usage: the two LLRF systems don’t power on at the same time, so the value of phase accumulator in the DDS may be different from each other, this will result in a phase difference between the two LLRF system.

The phase problem may be solved by modifying the hardware system, such as: 1. using a UPS as the power supply of the clock reference board and the signal control boards; or 2. add another reset signal to the two DDSs in the signal control boards; or 3. use another power switch to make sure the two systems power on at the same time. But these methods may need hardware modification. Therefore, it not the most cost-effective way to the designer. An alliterative way to make sure the system has a correct phase after the power is on is to use a software strategy to solve this problem. In short, the system will use the DDS as a phase shifter to search and validate the phase of the two system. The relevant phase-control circuits are marked with orange color in Fig. 1.

When the two pick up signals from two cavities are in phase with respect to the phase-reference signal, the phase error of the two cavities are zero degree. In this case, the phase detector gives a zero output value. Things would be easy if the phase detector gives only one zero point in [0, 2π]. But, in fact, the digital phase detector has a non-monotonic region, which has another zero point. The phase-control loop prefers the usable range of the phase detector to be as large as possible, so it can close the control-loop at any point. Meanwhile, the phase align procedure prefers the phase detector has only one zero point. Thus, the hardware of the phase detector has to be optimized to reduce the non-monotonic region as much as possible.

2.1 Digital phase detector

The 2π edge-triggered phase detector is used in the phase control board due to the output voltage of the 4π phase detector is not favorable for this application [18]. A limiter is used to extend the dynamic range of the phase detector. The core of the digital phase detector consists of two ECL logic D flip-flops and an exclusive NOR gate. The duty factor of the exclusive NOR gate output is proportional to the phase error. The digital output signal goes through a low-pass filter to generate a DC voltage. The circuitry is shown in Fig. 2(a) and the timing diagram is shown in Fig. 2(c). This phase detector belongs to TYPE-II edge triggered three state phase detector and its operating range is [0,2π]. In theory, the output of the circuit is given by [19]:

Figure 2:Full-screen View

(Color online) Function block and timing diagram of the phase detector.

$V_{\text{out}}=K*V_{\text{od}}*\frac{P{W}_{\text{up}}-P{W}_{\text{down}}}{P{W}_{\text{f}}}\mathrm{,}$ (1)

where, K is the gain factor, which can be adjusted by changing the resistor in the feedback loop of the OPAMP. V_od is the output voltage level. PW_f is the pulse width of the input RF signal.

Because of the switching times of the D flip-flop, near zero degree, the circuits involved in phase detection can be equivalent to Fig. 2(b). The timing diagram of the circuits(as in Fig. 2(b)) is shown in Fig. 2(d). Compared to the normal mode in Fig. 2(c), it is obvious that the D flip-flop can not distinguish the two clocks and treats them as one clock in U(0,δ). But the output of the D flip-flop (Q1 and Q2) is still proportional with respect to the input phase error in U(0,δ) and the duty factor is changed. Therefore, in the inside region where ϕ ∈ U(0,δ), the transfer function of the circuit is different from Fig. 2(a). When the phase goes into the boundary near δ, the circuits begin to transfer from one to the other one. In this region, not only the output amplitude will be affected but also the monotonicity may not be guaranteed (as in Fig. 4). An oscilloscope screen snap, which contains of the RFA, RFB, Q1, and Q2 signals, is shown in Fig. 3. The snap is taken when the detector is entering the region and oscillating in between the two equivalent models, which are shown in Fig. 2(a) and Fig. 2(b), respectively.

Figure 4:Full-screen View

(Color online) Comparison of the hardware optimization.

Figure 3:Full-screen View

(Color online) The output of the phase detector in the dead zone.

To minimize the range of the non-monotonic region, the hardware has been optimized for three aspects: a) change the location of the pull-up resistances closer to the D flip-flop; b) change the exclusive NOR gate to a faster one; c) change the D flip-flop to a faster one. Fig. 4 gives the results and comparisons before and after these optimizations.

After the optimization, the non-monotonic region is ϕ ∈ [0,π/6] ∪ [1.9π,2π]. There is a zero point in this region, which is an unfavorable point for phase-control. According to the hardware optimization, the non-monotonic region is determined by the input signal frequency and the manufacturing technique of the D flip-flop and the NOR gate, especially the switching times(e.g. raise and fall time, the propagation delay) of the chips. The switching times of the D flip-flop would not be eliminated, so the non-monotonic region would exist all the time. The hardware optimizations can only reduce the non-monotonic region and can not eliminate it. Using a software method to solve this problem may be easier than continuing to optimize the hardware.

2.2 Auto phase matching

In order to reduce the influence of the non-monotonic region and generate a closed-loop control in the linear region, the LLRF control system uses an automatic phase matching technique. The essence of this technique is an algorithm based on the decision tree. The decision tree [20] is one of the most commonly used and supervised learning classification techniques in the machine learning filed. The classifier analyses the training data first, then constructs the classification rules (decision tree), and then classifies the dataset using the rules. The construction procedures are: 1. Collect the phase-voltage value samples of the phase detector using DDS and ADC. 2. Plot the phase-voltage curve of the phase detector and fit the phase detection function y=f(ϕ). Comparing the function with the ideal function $u=k*\varphi +b(\varphi \in [\mathrm{0,2}\pi ]\mathrm{,}b\in ℝ$) and get the non-monotonic region of the detector ϕ ∈ U(0,δ). 3. Disperse the dataset as Table 1 shows. Each sample consists of three features and a label. 4. The information for symbol xi, which can take on multiple values, is defined as

Table 1:Full-screen View

Data of Phase Detector.

Sample	Zero?	In Region (ϕ0-δ,ϕ0), Linear Value?	In Region (ϕ0,ϕ0+δ), Linear Value?	Zero Point?
1	Yes	No	No	No
...*	Yes	No	No	No
	Yes	No	No	No
	No	Yes	Yes	No
...*	No	Yes	Yes	No
	Yes	Yes	Yes	Yes
...*	Yes	Yes	Yes	Yes
	Yes	Yes	Yes	Yes
...*	Yes	Yes	Yes	Yes
	Yes	Yes	Yes	Yes
	No	Yes	Yes	No
...*	No	Yes	Yes	No
	Yes	No	No	No

Show more

* These data are omitted.

$l(x_i)={{\displaystyle \log }}_{2}p(x_i)\mathrm{,}$ (2)

where p(xi) is the probability of choosing a class.

The Shannon entropy is the expected value of all the information of all possible values of the class. This is given by

$H=-{\displaystyle \sum _{i=1}^n}p(x_i)*l(x_i)\mathrm{,}$ (3)

where n is the number of classes.

Calculate the Shannon entropy of the dataset in step 3, compare the information gain among all the features and return the index of the best feature. Splitting the data set based on the best feature and forming a branch. 5. Calling the step 3 recursively until all the instances in a branch are in the same class. 6. Plotting the decision tree. 7. Testing the decision tree. 8. Realizing the algorism on DSP and classifying the phase difference voltage online.

The decision tree in step 6 is shown in Fig. 5. According to the decision tree, the procedures in step 8 are: shifting the phase of the output signal step by step and reading the output voltage of the phase detector. Each step is 0.1 degree. This step won’t stop until the zero point (ϕ_zero, 0) is found. But in fact, the ADC may be effected by noise signal, which then the absolute zero point could’t be found easily. Instead, the algorism tries to search a set of points (ϕ_zero,{x||x<0.01}). Once it finds one point to satisfy the rules, it will switch to a closed-loop PID control, which will take care of the small phase difference between the points (ϕ_zero,{x||_x|<0.01}).

Figure 5:Full-screen View

Decision Tree of Auto Matching Algorism.

After finding a zero point, judge the linearity of the data in ϕ ∈ U (ϕ_zero,δ). If the output of the detector in ϕ ∈ U (ϕ_zero,δ) is non-linear, then drop this zero point and keep on searching, or else the searching procedure is over and returns to the zero phase to the PID controller. Then the phase of the two cavities is correct right after applying power to the cavities and the PID controller generates a closed-loop control of the cavity phase.

The linearity of the output in ϕ ∈ U (ϕ_zero,δ) is determined as follows: splitting the region into two regions: ϕ ∈ (ϕ_zero-δ,ϕ_zero∪ (ϕ_zero,ϕ_zero+δ). Calculate the rake ration of the line determined by the two terminal points and compare it with the idle rake ration of the phase detector. If the two rake rations are almost equal, the value of the phase detector is leaner; the other results are non-linear in this region.

The time complexity of the auto matching algorism is calculated as follows: the time complexity of the linear judgment program is O(n) and its condition is 2/n; the time complexity of the phase shift program is O(n), so the time complexity of the algorism is O(n).

3 Experiment and discussion

To evaluate the performance of the algorism, it was tested with the RF system of the CYCIAE-100 cyclotron. The online test is under the condition of full RF power, 32 kW. To minimize the influence of the transmission cables to phase error, the oscilloscope is placed on the top of the cyclotron. Two pick up signals from the two independent cavities are chosen as the input signal for test. These two signals go through two same length(two meters) RG223 transmission cables to the Agilent DSO6054A oscilloscope. The measuring position and equipment with their transmission cables are shown in Fig. 6. This bench test is aimed to test the phase matching time and the residual phase error of the system. After several tests, the measurement results shows that the auto phase matching technique can align the phase of the two cavities automatically within 30 s and the residual phase error is approaching the under measurement limit of the oscilloscope, as shown in the zoomed in part of the oscilloscope in Fig. 6. The phase error is later measured by a dynamic signal analyzer and the result shows the phase control precision is about 0.08 degrees.

Figure 6:Full-screen View

(Color online) Online test of the auto phase matching technique.

On July 4, 2014, the first 100 MeV proton beam was extracted out of the cyclotron. On July 25 of the same year, the CYCIAE-100 cyclotron maintained its beam at about 25 μ A for about 9 hours [21]. In the first year of operation, there were more than 20 times of scheduled shut down of the cyclotron system. For each time when the cyclotron RF system is completely shutdown. When the cyclotron is powered on again, the operator confirmed that the phase matching of the two cavities can be done automatically within 30 seconds, usually 20 seconds. If the operator turn off the automatic phase matching function, the phase of the two RF system may not satisfy the requirements of beam acceleration. An oscilloscope screen snap in this situation is shown in the left bottom of Fig. 6.

Increasing the phase step in the searching state may reduce the matching time. After the DC output value of the phase detector is smaller than 0.5 V, the algorism switches to the fine control of the phase to search the zero point. This would be a effective way to reduce the searching time in the monotonic region. This is the fastest algorism till now, we will keep on studying the algorism or try other algorisms to make it faster in the future.

4 Conclusion

The CYCIAE-100 cyclotron take a software technique to match the phase of the two cavities. The phase detector has been optimized for three aspects to reduce the non-monotonic region. Then, an automatic phase matching technique based on the decision tree is used to avoid the influence of the non-monotonic region to the phase-control loop and match the phase of the two cavities automatically. This technique is successfully used in the CYCIAE-100 cyclotron RF system. It matches the phase of the RF cavities in 30 seconds and the phase control precision is better than 0.08 degree. This technique not only provides experiences for the tuning loop of the CYCIAE-230 cyclotron, but also can be used in the similar cyclotron RF system.