Experimental device description

The CSOI devices utilized in the experiments were fabricated using the 0.18 μm FDSOI process, and the primary parameters and transistor sizes are listed in Table 1. The overall structure comprised two silicon layers (SOI1 and SOI2) and two oxygen-embedded layers (BOX1 and BOX2). Electronic components were fabricated on the top silicon film, whereas the intermediate silicon layer, SOI2, was positioned between the two oxygen-embedded layers to serve as a back-gate electrode. This electrode enabled adjustment of the electrical performance and resistance of the device to SEUs by modifying the voltage applied to SOI2. Consequently, both the electrical characteristics of the device and SEU resistance could be tailored by varying the voltage of SOI2. The presence of the BOX layer mitigated the parasitic bipolar amplification effect and decreased leakage currents.

A 4k-bit 6T-SRAM provided by the Institute of Microelectronics of the Chinese Academy of Sciences (IMCAS) was employed to explore the SEU resistance of SRAM fabricated using the CSOI process under varying back-gate biases. The chip package, which houses a 64 × 64-bit memory array with dimensions of approximately 1.45 mm × 1.45 mm, features a bit cell footprint of 10μm × 8 μm. Within the memory cell, N-type transistors share an NSOI electrode, denoted by V_nsoi, whereas P-type transistors share a PSOI electrode, denoted by V_psoi. The back-gate biasing of the SRAM ranges from -10 to 10 V. The circuits were encapsulated in DIP-28 packages. Considering the utilization of high-LET heavy ions in the experiment, the devices were decapped to ensure adequate penetration of the heavy ions.

Experimental setup for heavy-ion irradiation

For the experiments, Ta ions were selected from the TR5 terminal at the Heavy Ion Research Facility in Lanzhou (HIRFL) and the High Energy Heavy Ion Radiation Terminal (HERT) at the Space Environment Simulation and Research Infrastructure (SESRI) at Harbin Institute of Technology. The ion parameters are listed in Table 2, with the fluence set to 5×10⁶ ions/cm² for each experimental group. To achieve a uniform heavy-ion beam within the irradiated area, we adjusted the scanning current and frequency, coupled with precise control of the irradiated area by manipulating the slit size. Ta-ion irradiation was conducted in air, which was facilitated by the ability of the heavy-ion beam to reach the sensitive region of the device even after passing through a Ti window and traveling several microns in the atmosphere. The heavy ions traversed through a vacuum/air transition foil before impinging on the device. To detect the injection, we positioned an injection detector along the ray trajectory before the device under test. The LET of the ions from the device surface to the detector was adjusted by either inserting an energy attenuator (aluminum foil) into the trajectory of heavy-ion incidence or employing angled ion impingement.

Experiments were conducted to investigate the impact of NSOI and PSOI electrodes, as well as the power supply voltage, on the SRAM SEUs. Before irradiation, 55+AA-type data were pre-written into the SRAM memory cells with a dynamic reading of the SRAM memory content during irradiation. Any discrepancies between the read and write results were recorded by the test system as either a 0-1 or 1-0 upset, depending on the type of upset observed. These experiments were performed at room temperature while maintaining a flux of approximately 15000 ions/cm²·s to negate flux effects. A nominal supply voltage of 1.8 V was applied to the test system to simulate the normal operating state of the device. Back-gate biases were uniformly set to zero to assess the effect of the supply voltage on SRAM SEU. Six supply voltage biases were selected: pull down 20% (1.44 V), pull down 10% (1.62 V), pull down 5% (1.71 V), nominal voltage (1.80 V), pull up 10% (1.98 V), and pull up 20% (2.16 V). These biases were selected to examine the effect of the supply voltage on SEU.

The SEU overturning cross section is calculated as ${\sigma }_{\text{seu}}=\frac{N_{\text{event}}}{\text{fluence}\times N_{\text{bit}}}$ (1) where N_event is the total number of SEUs, and N_bit and fluence are the SRAM memory cell capacity and experimental injection, respectively [29].

TCAD Physical Model Setting

To achieve a comprehensive understanding of the mechanisms driving the observed experimental phenomena, we employed TCAD semiconductor device-simulation software to develop a CSOI model. After parameter calibration, we utilized SDEVICE to construct a 6T-SRAM for the CSOI process. This section presents an investigation of the relationship between the SEE and parameters such as the heavy-ion incidence position, back-gate voltage, and supply voltage to elucidate the phenomena detailed in Section 3.

Figure 3 depicts the CSOI device model developed for this simulation. The SRAM core memory cell comprised two pairs of input and output cross-coupled inverters (N1, P1; N2, P2). In the stable storage state of the cell, the word line was maintained at a low level, causing the transmission transistors N3 and N4 to be in the off state. Consequently, the n0 node stored datum “1”, whereas the n1 node stored data “0”.

Fig. 3Full-screen View

(Color online) CSOI Device Models

Heavy-ion incidence was modeled by incorporating lateral diffusion via a Gaussian distribution with a trajectory radius of 0.015 μm. Given the significant generation of carriers due to SEEs, mechanisms including Fermi–Dirac statistics [30] as well as Shockley—Read–Hall (SRH) and Auger recombinations [31] (indirect and Russo–Cherese composites) were incorporated into the simulation. $R_{\text{net}}^{\text{SRH}}=\frac{np-n_{i\mathrm{,}\text{eff}}^2}{{\tau }_{\text{p}}\left(n+n_1\right)+{\tau }_{\text{n}}\left(p+p_1\right)}$ (2) Carrier transport was resolved through the application of a hydrodynamic model, which entails the concurrent coupling of the electron and hole temperature equations. The Philips unified model (PhuMob) was employed to consider the collective influence of phonon scattering, inter-carrier scattering, and ionizing impurity scattering on mobility [32]. $\frac{1}{{\mu }_{i\mathrm{,}\text{b}}}=\frac{1}{{\mu }_{i\mathrm{,}\text{L}}}+\frac{1}{{\mu }_{i\mathrm{,}\text{D}}}$ (3) The Enormal model incorporates the impact of the electric field perpendicular to the interface on mobility. The high-field velocity saturation mobility model (HighFieldSaturation model) integrates the correlation between the mobility and the electric field force, along with the saturation velocity [33]. Moreover, a resistive contact model was implemented at the source and drain terminals. Through introducing a distributed resistor (DistResist) between the contact and silicon surface of the device body, an external voltage induced a voltage drop across the resistive contact, thereby enhancing the realism of the device model.

Susceptibility of SEUs to the incidence position of heavy-ion

The simulation results indicated that the off-state transistor exhibited the highest sensitivity to SEUs, as shown in Fig. 4. In this state, electrons generated by heavy ions within the off-state NMOS channel swiftly migrated towards the drain owing to the carrier-collecting effect and bipolar amplification effect facilitated by the drain PN junctions. Consequently, the peak SET current reached its maximum magnitude. Conversely, in the transmission state, the source and drain terminals were biased, rendering them unable to establish a potential difference in the carrier drift. Consequently, only a minimal number of carriers migrated to the source and drain terminals concurrently owing to the diffusion motion, resulting in a significantly reduced SET current compared with the off state. In the open state, the electric potential difference between the source and drain was zero, impeding the drain from efficiently collecting the electron-hole pairs generated by the channel. Hence, the on-state NMOS transistor exhibited the lowest sensitivity to SEUs.

Fig. 4Full-screen View

(Color online) Dependence of SEEs on the device state. Supply voltage = 1.8 V, heavy-ion incidence location at the drain PN junction, LET = 86.1 MeV·cm²/mg

Figure 5(a) depicts the charge collected at the drain end of the device when heavy ions impinged vertically on the off-state NMOS and PMOS of the SRAM at various positions. The findings indicated that the sensitive region of the SRAM was at the drain–gate PN (D-G) junction of the off-state transistor. Given the similarity in the physical mechanism of triggering SEEs for both off-state transistors, this study exclusively analyzed the NMOS transistor.

Fig. 5Full-screen View

(Color online) (a) Number of charges collected by the device when heavy ions hit different locations of the CSOI NMOS and PMOS. Supply voltage = 1.8 V, heavy-ion LET = 86.1 MeV·cm²/mg. (b) Electric field strength at different positions of CSOI NMOS before heavy-ion incidence

As depicted in Fig. 5(b), compared with other regions within the body area, the depletion region of the D-G junction in the off-state MOS exhibited the highest electric field strength. Consequently, the device achieved the highest efficiency in collecting carriers generated by heavy ions incident on the D-G junction. Consequently, the resulting current pulse from the heavy ions impacting this region demonstrated the shortest peaking time and accumulated the most charge. Conversely, when the incident position lay within the source region, the carrier drift motion was required to overcome the potential barriers of both the source–gate (S-G) and D-G junctions for collection by the drain electrode. Consequently, the source electrode exhibited the lowest sensitivity to SEEs, with only a fraction of carriers generated by heavy-ion ionization undergoing drift motion. Instead, the majority contributed to a diffusion current driven by concentration gradients, characterized by an SET pulse current featuring a small peak but a significant tail current.

Conversely, owing to their higher electron mobility compared with that of holes, electrons are more readily collected by the drain, resulting in the generation of a pulse current. Consequently, the SEE sensitivity of NMOS, in which electrons constitute the majority carriers in the source–drain, surpasses that of PMOS. This discrepancy is evident in Fig. 5(a), where the peak charge collected by NMOS exceeded that collected by the PMOS.

Furthermore, as depicted in Fig. 6(a), to elucidate the mechanism of heavy-ion impact on transistor-level devices and subsequently analyze the effect of back-gate voltage on the SEU cross section, we simulated the electrostatic potential of the devices at three distinct moments: before (T1), during (T2), and after (T3) heavy-ion incidence. Figure 6(b) shows that heavy ions with sufficient LET striking the sensitive region of an NMOS transistor generated a significant number of carriers within the device. Electrons were predominantly collected by the drain, thereby reducing the drain potential, whereas the accumulation of holes after electron excitation increased the body potential. This reduction in the potential barrier between the body and source–drain induced a zero or even positive bias in the base–emitter junction of the parasitic bipolar transistor, thereby instigating a bipolar amplification effect that augmented the pulse current.

Fig. 6Full-screen View

(Color online) (a) Dependence of SET on particle incidence position. Supply voltage 1.8 V, heavy ions were all vertically incident, LET = 86.1 MeV·cm²/mg. (b) Simulated electrostatic potentials at different times in Figure (a); the results are shown in a one-dimensional cross section along the source–drain axis of the device

Relationship between SEU occurrence and back-gate bias

Figure 7(a) and (b) illustrate the variations in the cross-sectional potential distributions with the back-gate bias for NMOS and PMOS transistors after heavy-ion incidence, respectively. As |V_nsoi| and |V_psoi| increased, the drain barrier height increased, making it more challenging for electrons to traverse the D-G barrier and reach the drain. Consequently, fewer carriers were collected at the drain of the off-state MOS, thereby attenuating the parasitic bipolar amplification effect and decreasing the SEE sensitivity of the device. This augmented the self-recovery capability of the SRAM and elevated the LET threshold.

Fig. 7Full-screen View

(Color online) (a) NMOS potential distribution after heavy-ion incidence. (b) PMOS potential distribution after heavy-ion incidence. The supply voltage was 1.8 V. The heavy ions were all incident perpendicularly on the drain junction with LET = 86.1 MeV·cm²/mg

Figure 8 shows the relationship between the collected charge and back-gate bias. As |V_soi| increased from 0 to 10 V, the NMOS collected charge decreased by 2.22%, and the number of SEUs in the experiment decreased by 94.24%. The PMOS collected charge decreased by 0.43%, and the number of SEU in the experiment decreased by 83.78%. This observation supported the experimental finding that the inhibition of SEUs was more pronounced with V_nsoi than with V_psoi.

Fig. 8Full-screen View

(Color online) (a) Collected charge of off-state NMOS in SRAM cells at different V_nsoi values. (b) Collected charge of off-state PMOS at different V_psoi values. The supply voltage was 1.8 V. The heavy ions were all incident perpendicularly on the drain junction with LET = 86.1 MeV·cm²/mg

In addition, when analyzing the experimental data, we observed that the device exhibited the most significant charge reduction when the absolute value of |V_soi| increased from 0 to 2 V. The slopes of the curves in Fig. 1(a) and (b) are 5.24×10^-11 cm²/bi·V and 4.48×10^-11 cm²/bi·V, respectively, which were the highest among all the ranges. This suggests that this voltage level offered the highest rejection efficiency for SEU occurrences. Considering both the circuit power and SEU cross section, the back-gate bias combination of V_nsoi=-2 V and V_psoi=2 V was considered more suitable.

Impact of Supply Voltage on SEUs

Because the semiconductor power consumption is directly proportional to the square of the supply voltage, a viable strategy for minimizing power usage involves lowering the supply voltage. However, note that the susceptibility of the SRAM to SEUs is influenced by the supply voltage. Consequently, a comprehensive examination of the SEU sensitivity of CSOI SRAM across various supply voltage levels must be conducted. The SRAM soft error rate is described by the following model [34]: $\text{SER}\propto F\times A\times \exp \left(-\frac{Q_{\text{crit}}}{Q_{\text{Coll}}}\right)$ (4) where F is the particle fluence in particles/(cm²·s), A is the area of the sensitive region of the particle incidence circuit in cm², and Q_crit and Q_Coll are the critical and collected charges in fC, respectively [35-37].

According to the formula $Q_{\text{crit}}\approx C_{\text{n}}{V}_{\text{DD}}$, as referenced in [38], the critical charge depends on the specific circuit and device attributes and is primarily influenced by the node capacitance and supply voltage. The minimum charge necessary for SEUs increases with higher supply voltages, reducing the transistor-sensitive volume owing to the augmented critical charge. This phenomenon, where an increase in the supply voltage results in a decrease in the SEU cross section by elevating the critical charge, is denoted as mechanism I in this paper.

In contrast, the collected charge (Q_Coll) is a strong function of the particle LET value and supply voltage, which characterizes the number of carriers collected at the drain during heavy-ion incidence [39]. For MOSFET devices, the depletion-region thickness can be calculated using the following equation: $W={\left[\frac{2K_S{\epsilon }_0}{q}\left(\frac{N_{\text{A}}+N_{\text{D}}}{N_{\text{A}}{N}_{\text{D}}}\right)\left(V_{\text{bi}}+V_{\text{A}}\right)\right]}^{\frac{1}{2}}$ (5) where K_s denotes the semiconductor dielectric constant, ${\epsilon }_0$ denotes the vacuum dielectric constant, q denotes the electronic charge, V_A and V_D denote the acceptor and donor doping concentrations, respectively, and V_bi and V_A denote the semiconductor built-in and applied voltages at the drain junction, respectively. V_bi is calculated as follows: $V_{\text{bi}}=\frac{kT}{q}\ln \left(\frac{N_{\text{A}}{N}_{\text{D}}}{n_i^2}\right)$ (6) The thickness of the depletion region is directly proportional to the supply voltage. This relationship implies that as the supply voltage increases, both the electric field density within the transistor and the volume susceptible to depletion increase. Consequently, the charge collected by the nodes increases. Figure 9 presents the current density in the NMOS drain region at various bias voltages. The supply voltage plays a significant role in shaping the characteristics of the PN junction depletion layer. Specifically, a higher voltage bias in the off-state NMOS drain results in a more pronounced electric field within the depletion region, enhancing the ability of the drain to collect drifting carriers. The peak node pulse current is primarily determined by the carrier drift. Therefore, an increase in the supply voltage intensifies the drift motion, resulting in an increase in the peak pulse current.

Fig. 9Full-screen View

(Color online) Effect of supply voltage on the depletion-layer current density. Supply voltage 1.8 V, heavy-ion incidence location at the drain PN junction of the off-state NMOS in SRAM cells

In the low core voltage state, the limited number of holes generated in the body region by low-LET heavy ions fails to effectively diminish the source–body potential barrier. Consequently, these holes are unable to traverse the depletion region between the source and body and are released through the ground. The accumulation of holes in the body region elevates the electric potential, prompting a significant flow of electrons to be collected by the drain through the depletion region between the drain and body. Conversely, heavy ions with high LET values generate a significant number of carriers, which significantly reduces the potential barriers between the source and body. Thus, most of the holes generated in the body region by these heavy ions cross the depletion region between the source and body and are released to the ground. This lowers the electric potential of the body region, suppresses the bipolar amplification effect, and results in partial electron collection by the drain. Therefore, in the low-voltage state, the current density produced by heavy ions with high LET values is lower than that produced by heavy ions with low LET values.

In the high-core-voltage state, the drain depletion region extends sufficiently to collect almost all the electrons generated by the low-LET heavy ions, causing the current density from these ions to saturate after the core voltage increases to 1.0 V. As the core voltage increases, the width of the drain-body depletion region expands, enhancing the electron collection efficiency of the drain. Simultaneously, the elevated drain voltage increased the electric potential of the body region, thereby strengthening the bipolar amplification effect. Consequently, the current density from heavy ions with high LET values increases rapidly with core voltage. In the high-voltage state, the current density from high-LET heavy ions surpasses that from low-LET heavy ions.

The physical process of widening the drain-junction depletion region owing to an increase in the supply voltage, as discussed in [40], results in the enlargement of the SEU cross section. This phenomenon is referred to as mechanism II in this paper.

Figure 10 shows that for low-LET heavy-ion incidence, Q_crit and Q_Coll increased with the supply voltage. However, the number of carriers generated by heavy ions of a specific LET value remained constant and was unaffected by variations in V_DD. The depletion region expanded sufficiently to capture the excited carriers when the supply voltage exceeded 1 V. Therefore, when the increase in V_DD allowed the drain–depletion region to gather the majority of carriers, the magnitude of the change in Q_crit and Q_Coll with respect to V_DD resulted in a notable disparity. This was evidenced by the increase in Q_crit surpassing the increase in Q_Coll. During this phase, mechanism I prevailed, resulting in a decrease in the SEU cross section with an increase in the supply voltage.

Fig. 10Full-screen View

(Color online) Variation in collected charge and critical charge with supply voltage was investigated for different LET values for heavy ions vertically incident on the drain junction of off-state NMOS in SRAM cells

However, for high-LET heavy-ion incidence, as shown in Fig. 10, because of its capacity to deposit a greater amount of energy in the sensitive region of the device, the excitation carriers were not entirely collected by the depletion layer at a voltage of V_DD of 1.98 V. The collected charge increased rapidly with increasing V_DD. At this juncture, Mechanism II was dominant.

During the competition between the two mechanisms mentioned above, the notable increase in the SEU cross section of CSOI SRAM under Ta-ion irradiation with increasing supply voltage can be attributed to the increase in the depletion layer thickness and the parasitic bipolar current induced by the increasing V_DD. Although mechanism II prevailed in this 0.18 μm node test and simulation, the conflicting influences of mechanisms I and II in small-node technology and low-core voltage scenarios merit further comprehensive investigation.