3.1 The Sampling Cell

As shown in Fig.1, the sample cell consists of two switched capacitors (one each in Block A and B) and a readout buffer. In total, 32 sampling cells are integrated for each channel.

Switches $S_{1A}-S_{1A}^{\text{'}}/S_{1B}-S_{1B}^{\text{'}}$ are used for sampling and $S_{2A}-S_{2A}^{\text{'}}/S_{2B}-S_{2B}^{\text{'}}$ for transferring. Switch $S_3$ is used for resetting the readout buffer. Complementary switches are used with an n-channel and a p-channel transistor connected in parallel. Bottom plate sampling ^[21] is adopted to reduce the input-related charge injection and to achieve better linearity performance. The sampling cell was simulated by the Spectre and the residual voltage could be reduced from 0.6 mV with a no time delay between ${\phi }_1$ and ${\phi }_1^{\text{'}}$ to 0.1 mV with a proper delay between ${\phi }_1$ and ${\phi }_1^{\text{'}}$. The non-overlap control signals, which are insensitive to CVT (corner, voltage, and temperature), are generated by the circuits shown in Fig.2.

Fig. 2Full-screen View

The schematic of the non-overlap control signal generator.

The structure of the readout buffer is also shown in Fig.1. The simple two-stage structure was used to save the power consumption and area, as well as to meet the speed and precision requirements. The settling time and input referred noise of the buffer were simulated to be 250 ns and 0.49 mV, respectively.

3.2 The Storage Cell

The schematic of the storage cell with the common current mirrors and comparator in ADC is shown in Fig.3. It consists of a switched capacitor and two common drain (source follower) transistors ($M_1$ and $M_2$) with switched outputs. Each storage block integrates 32 storage cells and each channel integrates 32 blocks, forming a 1024-cell event buffer.

Fig. 3Full-screen View

The schematic of the storage cell with the common current mirrors and comparator in ADC.

The storage cells are divided into two groups, corresponding to the sampling block A and B. The write of the storage cell (from sampling cell to storage cell) is then selected by the Block A/B selection line ($S_5$) and a 5-bit address line ($S_6$). The read of the storage cell (selected for digitization) is selected by a 6-bit address line ($S_7$). Two source followers are used to buffer the stored analog voltage and ramp signal, and the selected outputs are sent to the inputs of the comparator in the Wilkinson ADC. The two source follower transistors are placed closed to each other for better matching and reducing the influence from the environment. Each cell needs a pair of current mirrors that are shared among different storage blocks. In total, 32 pairs of current mirrors are integrated for 32 Wilkinson ADCs working in parallel. The supply voltage of 2.5 V is used to achieve 1 V linear range.

3.3 The Wilkinson ADC

The Wilkinson type ADC has been adopted because of its low power consumption and circuit compactness. Each channel integrates 32 Wilkinson ADCs and hence, a whole storage block can be digitized simultaneously.

The ramp signal generator is shared by all the 32 ADCs, as well as the 11-bit counter. As described above, the ramp signal is sent to each storage cell as the input of one source follower. The counter starts counting as the ramp signal rises, and its value is latched into a local 11-bit latch when the ramp signal crosses the stored voltage in the corresponding cell. The ramp signal sweeps from 0.2 V to 1.4 V in 12 μms. Here, an input voltage range of 0.3–1.3 V is used for better linearity. After digitization, the data is loaded into the output shift registers. The maximum output data bandwidth for ADCs is 29.3 Mbps per channel.

3.4 The Control Logic

The digital control circuit is developed using a standard digital IC design process. Only a few external signals are used to generate all internal control signals for sampling and storage of SCA, for example, sync for multi-ASIC synchronizing, trigger, read, move, and global reset. Three clocks are required: the sampling clock, ADC clock, and readout clock.

Two finite state machines (FSMs), SA and ST, are designed to control the sampling and storage SCA, respectively. The simplified state diagrams are shown in Fig.4.

Fig. 4Full-screen View

The state diagrams of the FSMs for (a) the sampling SCA and (b) the storage SCA.

The FSM SA has 4 different states:

SA1 – Block A sampling, Block B idle

SA2 – Block A transmitting data, Block B sampling

SA3 – Block A idle, Block B sampling

SA4 – Block A sampling, Block B transmitting data

The state transitions are driven by the trigger and full signals. The latter is an indicator whether the storage SCA blocks are full. There is no more response to the external triggers once all the storage blocks are full. In each state, the corresponding control signals are generated for the switches in the sampling cells (Fig.1). For instance, in State SA1, switches $S_{1A}-S_{1A}^{\text{'}}$ are turned on for each sampling cell in sequence with a duration of one sampling clock. Once a trigger is asserted, the state transits to SA2. Now, the switches $S_{1A}-S_{1A}^{\text{'}}$ are turned off and switches $S_{1B}-S_{1B}^{\text{'}}$ are turned on for each cell in sequence. At the same time, switches $S_{2A}-S_{2A}^{\text{'}}$ are turned on and switches $S_3$ are turned off for all sampling cells.

The FSM ST also has 4 different states:

ST1 – Waiting data from Block A

ST2 – Writing in data of Block A

ST3 – Waiting data from Block B

ST4 – Writing in data of Block B

In each state, the corresponding control signals are generated for the switches $S_5$ and $S_6$ in the storage cells (Fig.3). The external trigger signal generates control signals AW and BW, which are used to drive the state transitions along with signal full.

Control signals read and move are used for digitization and output data buffering. Signal read is used to start the AD conversion of the storage block that is currently selected, and signal move is used to shift the address to the next storage block. The digitized data is also loaded into the output shift registers at the end of the read operation. Flexible readout schemes can be implemented by an independent combination of these two signals. After digitization (read + move) or abandonment (move), the flag of the corresponding block is cleared, which otherwise may alter the indicator signals full and empty. The data can be shifted out by enabling the readout clock and signal read enable.

3.5 Layout design

The layout of the chip with a dimension of 4960 µm × 3980 µm is shown in Fig.5. The control logic is at the top and the analog bias generator is at the bottom. Each channel consists of the sampling SCA, storage SCA and Wilkinson ADC with output data buffer as shown in Fig.5. from the left to the right. The storage array occupies the largest area with a large number of MIM capacitors. A careful layout has been considered to suppress the interference of the digital circuits on the analog circuits.

Fig. 5Full-screen View

The layout of the GERO chip.

4.1 The Evaluation System

A dedicated evaluation board and FPGA test system have been developed to characterize the GERO prototype chip. The GERO chip was mounted on the evaluation board with 3 channel input signals via the SMA connectors. The external control signals were connected to the FPGA board through an adapter board, for 1.8 V to 3.3 V logic level conversions. The sampling frequency could be programmed through the remote bus control protocol (RBCP), as well as the event size and depth. The output data from the GERO chip was buffered in the FPGA before transferring to the computer via Ethernet. A Qt-based data acquisition software has been developed to configure the FPGA and to collect the data.

4.2 Functional Test

Configurations of different sampling rates from 25 MS/s to 100 MS/s, and event sizes from 32 to 1024 have been tested. A maximum data bandwidth of 800 Mbps has also been verified with 200 MHz readout clock. All the functions in the GERO chip, that are sampling, storage, data digitalization, and data output worked well; which means that the two stage SCA architecture, Wilkinson ADC, output shift registers, and control logic were running well. Fig.6 shows two examples of the waveforms with two different memory depths of 32-cell and 64-cell. The waveforms were far from satisfactory, but they could verify the flexible split of the memory depth.

Fig. 6Full-screen View

Waveforms of GERO sampling sin waves with (a) 32-cell memory depth (b) 64-cell memory depth

However, nearly half of the storage SCA blocks were found to have failed due to the mistakes in the layout. The outputs of these blocks were noisy and were independent to the inputs, and thus were discarded in the following analysis.

4.3 The Power Consumption

The power consumption of the GERO was measured at the room temperature with a main bias current of 50 µA. Two supply voltages of 1.8 V and 2.5 V were used. The power consumption was measured to be 2.3 mW/ch for the 1.8 V power supply, and 7.23 mW/ch for the 2.5 V power supply. The latter was much higher than the simulation result of 1.8 mW/ch. The ramp signals for the Wilkinson ADCs were found to be considerably steeper and their start points were approximately 100 mV higher than the designed values, accounting for the additional current of 0.5 mA per channel. Abnormal parasitic current paths were found from 2.5 V supply to ground, probably through some switch transistors in the ramp generator. The test results shown below are for less than 100 MS/s sampling and 1024-cell event size.

4.4 The Static Noise

The output noise was first tested by measuring the output variances, during sampling different DC voltages. A typical histogram distribution of the digitized outputs for a certain storage cell sampling a DC level is shown in Fig.7(a). In total, 5000 samples were collected for each histogram. The input referred noise was then estimated to be 1.2 mV from the standard deviation of the major peak, which is consistent with the simulation result of 1.17 mV. However, a minor peak could also be clearly seen, which was common for quite amount of storage cells. The differences between the major and minor peaks varied for different input voltages. The phenomenon of the twin peak was most probably caused by the disturbance on the ramp signal. Only the major peaks were used for the static performance evaluation.

Fig. 7Full-screen View

The GERO test results of (a) the output distribution for a certain storage cell for the input voltage of 0.8 V (5000 events collected), (b) the measured ASIC outputs vs. DC input voltages (top) and the INL (bottom), (c) the change of the ASIC output vs. waiting time before readout, (d) the DC responses of the different storage cells in one channel with their linear fits, (e) the transient waveforms recorded by GERO with their Lorentz fits. The sampling period between two adjacent sampling cells is 10 ns; the figures illustrate the outputs with sampling cell as well as time.

4.5 The Linearity

The mean values of the major peaks for different DC input voltages are shown in Fig.7(b), along with the linear fit curve. The linear range was reduced to 0.4–1.25 V, because of the exceptional leakage current in the ramp signal. The maximum integral non-linearity (INL) was typically around 3% for the input range. Besides the issue of the ramp signal, the major source of the non-linearity was from the pair of the source followers, according to the circuit simulation. This could be improved in the future by optimizing the size of the source follower transistors (e.g. 8 u/1 u) and by changing the output point to the other side of the switch $S_8$ (N in Fig.3). According to the simulation results, the INL of the updated structure decreased blow 0.1%.

4.6 The Leakage Current

The charge loss caused by the leakage current could be significant, especially for a large SCA. The major contribution to the leakage current was from the switch transistors and was voltage dependent. The change of the ASIC output versus time for 1.2 V input voltage is shown in Fig.7(c). The leakage current was calculated to be 260 fA. At the readout frequency of 200 MHz, the difference caused by the leakage current between the first and the last block is less than 1 mV.

4.7 The Non-Uniformity

The DC responses of the different storage cells in one channel were measured for 0.7–0.9 V input range. In total, 544 cells were tested; and for each cell three different input voltages were repeatedly sampled for 1000 times. The averaged sample points with their linear fits are shown in Fig.7(d). The standard deviation of the offsets was 20.4 mV. This is almost one order of the magnitude larger than the simulation result of 2.43 mV, indicating abnormal contributions probably due to the unstable ramp signal. In the next version, the mistakes relating ramp generate circuit would be corrected, and a bandgap will be used instead of a current mirror to generate a more stable and reliable ramp signal.

4.8 The Transient Performance

The quantitative measurement of the dynamic performance became extremely difficult due to the unexpected problems such as half-failed storage cells and twin peak phenomenon. However, to prove the functionality of the GERO chip, Lorentz waves with two different amplitudes were sampled at 100 MS/s, as shown in Fig.7(e). The baseline of the Lorentz waves was 550 mV, and the peak values were 700 mV and 1000 mV, respectively. The FWHM width of the Lorentz waves was approximately 575 ns, and the waves occupied seven consecutive storage blocks.