Charge-sensitive amplifier with fast-reset circuit

To maximize the coverage of the outer surface of the pCsI crystal and capture more fluorescence, the STCF ECAL used APD detectors (S8664-1010, Hamamatsu, Japan) with a large sensitive area of 10 mm×10 mm. However, the substantial sensitive area of the APD introduces challenges to the front-end readout circuit in terms of noise and speed-performance optimization, because of its large detector capacitance (typically C_D=270 pF) and leakage current (typically $I_{\text{D}}=10\text{ nA}$). The equivalent noise charge (ENC) was calculated using Eq. (1). The ENC contributions due to the current parallel, thermal, and flicker noises are expressed in (2), (3), and (4), respectively [25]. $EN{C}_{\text{t}}=\sqrt{EN{C}_{\text{i}}{}^2+EN{C}_{\text{w}}{}^2+EN{C}_{\text{f}}{}^2}$ (1) $EN{C}_{\text{i}}{}^2=\left(\frac{4kT}{R_{\text{f}}}+2q{I}_{\text{D}}\right)\cdot \frac{t_{\text{p}}}{q^2}\cdot N_{\text{s}}$ (2) $EN{C}_{\text{w}}{}^2=\frac{4kT\gamma }{g_{\text{m0}}}\cdot \frac{{\left(C_{\text{D}}+C_{\text{f}}+C_{\text{P}}\right)}^2}{q^2{t}_p}\cdot N_{\text{w}}$ (3) $EN{C}_{\text{f}}{}^2=\frac{K_{1/f}}{C_{\text{ox}}WL}\cdot \frac{{\left(C_{\text{D}}+C_{\text{f}}+C_{\text{P}}\right)}^2}{q^2}\cdot N_{\text{f}}\mathrm{,}$ (4) where R_f is the feedback resistance of the CSA (implemented by an n-MOSFET working in the subthreshold region), I_D is the leakage current of the APD, t_p is the peaking time of the shaper, $g_{\text{m0}}$ is the transconductance of the input transistor M₀, W and L are the width and length of the input transistor M₀, respectively, C_D is the capacitance of the APD detector, C_f is the feedback capacitor of the CSA, and C_P is the parasitic capacitance excluding C_D at the CSA input node. The parasitic capacitance C_P is proportional to W and L. γ and $K_{1/f}$ are the thermal and flicker noise coefficients, respectively. N_s, N_w, and N_f are constants for parameter n of the shaper. To mitigate the impact of a large capacitance on the readout circuit, a high-gain, wide-bandwidth, low-noise, single-ended input split-leg cascade amplifier with dual common-gate stages is proposed [12, 13]. The input NMOS is optimized to operate in the moderate-inversion region (between strong and weak inversion) with a gate length (L) of 1 μm, gate width (W) of 16 mm (20 μm×800 fingers), and bias current of 8.2 mA to achieve a high transconductance (g_m0=125 mS) for reduced thermal noise [26].

As the input-current pulses accumulate charge on feedback capacitor C_f, the output voltage of the CSA gradually increases, eventually leading to saturation. To prevent the saturation of the amplifier and provide a stable DC operating point, a reset block must be connected in parallel to the feedback capacitor C_f. Two basic techniques have been implemented to discharge the feedback capacitance: switch reset and continuous discharge [15, 27]. The switch-reset technique discharges the feedback capacitor by periodically opening a switch. The disadvantages of this solution are sampled noise and charge injection from the switch transistor. Additionally, each reset of the CSA introduces a negative signal to the shaper, thereby increasing the dead time of the readout circuits. Although a resettable shaper structure can overcome this negative signal, it increases the complexity of the system [17].

The continuous-discharge technique can be applied using a resistor (or an equivalent circuit) parallel to C_f to achieve continuous discharge of the accumulated charge [28]. The output waveform of the CSA in this mode is shown in Fig. 3. The rise time t_rise is affected by two factors: T_d and T_GBP. The time constant T_GBP depends on the gain-bandwidth product (GBP) of the core amplifier [13]. The value of the feedback resistor (R_f) must be sufficiently large to reduce ballistic deficit effects and simultaneously minimize the impact of its parallel noise. Typically, an MOS transistor operating in a triode or saturation region is employed as the feedback resistor. This is a compact solution that may enable the control of feedback resistance; however, nonlinear effects must be considered. The long decay-time constant (τ_f = R_f×C_f) of the preamplifier output signal imposes limitations on the count rate owing to pulse pile-ups. When the resistance value of the feedback resistor R_f is reduced to decrease the CSA reset time $t_{\text{rst}}$ (approximately 4τ_f), the impact of the ballistic deficit and noise contribution from the feedback resistor Rf becomes non-negligible, affecting the overall noise performance of the circuit. Therefore, a compromise between noise and count rate is necessary in the design of R_f.

Fig. 3Full-screen View

(Color online) Charge-sensitive amplifier output-signal waveforms and associated time parameters

The energy distribution of the background events for the STCF ECAL is predominantly concentrated in the low-energy region below 1 MeV [2]. The magnitude of the event pulses was comparable to the equivalent noise of the front-end readout circuit. Thus, the influence of these background events manifests as an increase in the CSA output baseline, and the readout circuit cannot effectively detect these events. The event rate for higher-energy background events (≥10 MeV) is significantly reduced [2]. According to the energy distribution and average event rate (Poisson distribution) of the background events, the probability that background events of different energies occur in a 700 ns signal waveform can be estimated. For a barrel ECAL, the probability of more than one event greater than a 10 MeV background event within a 700 ns waveform width is only approximately 0.6%. Therefore, we can assume that a physical event will have only one larger background signal piled-up with it. As shown in Fig. 3, the output signals of the CSA can be piled up to a certain extent; thus, the circuit-receivable event rate can be increased. In this design, we added a saturation-detection circuit and fast-reset circuit for the CSA. When the CSA output reaches a preset saturation level owing to the event pile-up, a fast reset is launched to prevent the circuit from entering dead time.

A block diagram of the proposed CSA is presented in Fig. 4a. The core amplifier comprises two output branches formed by two source followers. One output (EOUT) is connected to the energy-measurement channel. The other output (TOUT) is connected to the time-measurement channel. The continuous-reset feedback resistor R_f is positioned between the input and EOUT, interfacing with the subsequent pole-zero cancellation circuit. The feedback resistor Rf implemented using the NMOS transistor M₁ has a resistance value controlled by the voltage RESCSA, with an adjustable equivalent resistance ranging from approximately 0.3 MΩto 60 MΩ. Under the condition C_f=500 fF, the decay time required for the CSA to recover to the baseline ranges from approximately 0.6 μs to 120 μs.

Fig. 4Full-screen View

(Color online) (a) Block diagram of the proposed charge-sensitive amplifier, (b) block diagram illustrating the fast-reset control circuit

The fast-reset feedback circuit is positioned between the input and TOUT to minimize its effect on the energy-channel signal. This circuit includes switch transistors M₂ and M₃, controlled by the FRST and NFRST (inverted signal of FRST) signals, along with a current-limiting resistor R_sw. The M₃ transistor is utilized to suppress the clock feed-through and charge-injection effects induced by M₂. The resistor R_sw restricts the reset current during the fast-reset process, ensuring the stability of the CSA [15].

The saturation-detection circuit employs a hysteresis comparator that generates a corresponding pulse signal when the CSA output voltage exceeds a certain threshold (near the saturation level). The circuit for generating FRST is shown in Fig. 4b, incorporating the FREN signal to control the operation of the fast-reset circuit. When FREN=1, the TR is buffered and fed into a monostable circuit, producing a fixed-width (40 ns) pulse signal FRST (as well as NFRST) and completing the fast reset of the CSA. The fast-reset circuit operates only when the CSA is piled up near its maximum, and any detected events during the fast-reset operation are discarded to guarantee the noise performance of the circuit.

High-order shaper with baseline holder circuit

In high-count-rate applications, the theoretically optimal peak time often falls short of meeting the count-rate requirements. In such scenarios, the noise performance with the count rate must be compromised by employing a small adjustable peak time. For example, in our study, the theoretically optimal peak time ranges from 0.51 μs to 2.58 μs (varying with the detector-leakage current and noise contribution from the feedback resistor R_f). However, to satisfy the count-rate requirement of 1.5 MHz, the maximum peak time is set to 204 ns (choosing a shaper order of n=6). In addition to reducing the peak time, similar to the output signals of the CSA, the shaper output signals can also pile-up to a certain extent. Thus, the detection of piled-up signals offers a solution for meeting the higher count-rate requirements.

As depicted in Fig. 5a, the width of the shaper output signal t_width is defined as the time range encompassing 1% to 1% of the maximum signal amplitude. The rise time t_rise represents the time required for the signal amplitude to increase from 1% to its peak, whereas the fall time t_fall represents the time required for the signal amplitude to decrease from its peak value to 1%. The rise t_rise and fall t_fall times primarily depend on the peak time t_p and the characteristics of the shaper (such as the number of real or complex poles). The peak-time points of the two signals are t₁ and t₂, respectively, and the time interval between them is denoted as t_delay.

Fig. 5Full-screen View

(Color online) Shaping-amplifier output-signal waveforms and associated time parameters

Conventionally, readout circuits operate with t_delay ≥ t_width, as shown in Fig. 5a. When t_delay < t_width, the phenomenon of signal pile-up can be observed. Two typical pile-up scenarios for shaper-output signals are illustrated in Fig. 5b and c. In both cases, the two input signals have equal charges (E₁ = E₂). t₁ and t₂ represent the peak time points when the two signals are inputted individually. t_pk1 and t_pk1 are the peak time points for the piled-up signal. Signals can still be considered effective when they increase by only 1% compared to the ideal peak-voltage amplitude. Thus, as shown in Fig. 5b, when t_delay ≥ $t_{\text{delay,th2}}$ ≈ t_fall, the voltage amplitude of the piled-up signal at the peak point t_pk1 is equal to the ideal peak-voltage amplitude. Additionally, the voltage amplitude of the piled-up signal at the peak point t_pk1 increases by only 1% compared to the ideal peak-voltage amplitude because the tailing part of the first signal does not overlap with the peak of the second signal; both of the signals are considered effective. As shown in Fig. 5c, when t_delay > t_delay,th1 ≈ t_rise, the voltage amplitude of the piled-up signal at the peak point t_pk1 increases by only 1% compared with the ideal peak-voltage amplitude because the leading part of the second signal does not overlap with the peak of the first signal, and the first signal can still be considered an effective signal. Note that when the two input signals have different charges, t_delay,th2 and t_delay,th1 change according to E₁/E₂ ratio [19]. Event timestamps can be obtained from the time channel; thus, t_delay between each signal is available. According to the time information, pile-up rejection (PUR) can be applied effectively in the back-end data-processing program to accept undistorted amplitudes and reject distorted amplitudes.

As shown in Fig. 6, the ratios of t_width to t_p and t_delay,th2 to t_p at E₁ = E₂ are depicted for different shaper orders. The values of t_width/t_p and t_delay,th2/t_p decrease significantly as the order n of the shaper increases. However, for n≥5, the decreasing trend gradually slows, and the improvement is insignificant. This illustrates that higher-order shaper circuits are more suitable for high-count-rate applications. However, considering the noise performance, with a fixed shaper output-signal width of t_width=667 ns corresponding to a count rate of 1.5 MHz (periodically distributed input signals), the thermal-noise coefficient $N_{\text{w}}/t_{\text{p}}$ exhibits a smaller value in the range $4\le n\le 6$. The shot-noise coefficient $N_{\text{s}}*t_{\text{p}}$ gradually decreases after n≥2. Thus, selecting a sixth-order shaper achieves noise optimization while meeting the high count-rate requirement. In this configuration, the ratio of the signal width to the peak time is approximately 3.28, and the ratio of the time interval between the input signals and peak time is approximately 1.8. For the count-rate requirement of 1.5 MHz, without considering the piling up of shaper-output signals, the maximum peak time is only 200 ns. However, allowing for the piling up of output signals, this shaper can extend the maximum peak time to 370 ns, thereby mitigating the degradation of noise performance.

Fig. 6Full-screen View

(Color online) Ratio of output-signal width t_width to peak time t_p and ratio of input-signal interval t_delay to peak time t_p for different filter orders

The proposed $\text{CR}-{\left(\text{RC}\right)}^6$ semi-Gaussian high-order shaper is shown in Fig. 7a. The shaper is composed of a CR-RC filter, multiple feedback (MFB) filter, Sallen–Key (SK) filter, and an RC filter. The front-end readout circuit collects electrons, resulting in a positive output signal from the CSA and subsequently produces a negative output signal in the CR-RC circuit. To guarantee a positive output signal and broaden the output range (with the baseline voltage established by the CSA and maintained at approximately 0.8 V), the second stage is identified as an MFB filter structure aimed at converting the signal output into a positive format. The SK filter is chosen for the third stage because of its properties as an in-phase proportional amplifier and its capacity for gain adjustment. The amplifiers for the CR-RC and MFB filters employ a single-ended input-output cascade structure similar to that of the CSA core amplifier, and the sizes of the individual transistors in the amplifier are carefully tailored to guarantee that the DC voltages of both the CSA and filters are nearly identical. In addition, utilizing an amplifier with an identical construction to supply a bias voltage at the negative terminal of the SK ensures that the DC voltages at both ends of the SK stage amplifier are balanced, thereby guaranteeing that the final output baseline remains stable around 0.8 V. The peak time is adjustable in this design and ranges from 120 ns to 1680 ns. A pole-zero cancellation (PZC) circuit is used to eliminate the undershoot of the shaper output and increase the event rate. The pole-zero cancellation resistor (M1) forms a DC path between the CSA and shaper. In the event of a pile-up of CSA output signals, a DC current I_IN flowing through the resistor network of the shaper induces a baseline drift in the output, impacting the amplitude-detection accuracy of the readout system. To address this issue, a BLH circuit is used to generate I_F to compensate for I_IN, thereby suppressing the baseline drift [29]. Figure 7b shows the transfer function of the BLH circuit during the operation (excluding M1 and $C_{1a}$). For effective signal frequencies, the gain is approximately 113.4 dB. For low-frequency signals (below 1 Hz), the gain is approximately 60.5 dB, representing a reduction of 52.9 dB in the low-frequency loop gain by the BLH circuit.

Fig. 7Full-screen View

(Color online) (a) Simplified schematic of the $\text{CR}-{\left(\text{RC}\right)}^6$ shaper with baseline holder circuit. (b) Simulation results of the transfer function of the BLH-shaper closed-loop system (excluding M1 and $C_{1a}$)

Peak-detection and holding circuit

The output signal of the shaper is connected to the PDH, which detects and holds the peak voltage of the signal. The choice and operation of the PDH influence the count rate and relate it to the operation of the PUR. Traditionally, the width of a PDH output signal consists of three parts: the writing time t_write, reading time t_read, and reset time t_rst,pdh. When only one PDH circuit is used, if a second signal with a higher (or lower) amplitude occurs in the same channel during the readout by the ADC, the first (or second) amplitude will be lost; therefore, at least two levels of storage depth are required for high-count-rate applications. Two different approaches are commonly used: resetting the PDH for a fixed time after peak detection, or keeping the PDH reset until the output of the shaper falls below a fixed threshold again. Both approaches have the probability to lose events, especially the piled-up signals of the shaper.

To enhance the event rate received by the PDH circuit, the storage depth must be increased and the dead time must be reduced. This study employs three strategies to minimize the dead time. First, two PDH submodules are employed to increase the storage depth. While one module operates during the writing interval, another operates during the reading interval. This ensures that one module is always waiting for the signal and the dead time introduced by the reading time t_read is eliminated. Second, the reset time t_rst,pdh is concealed within the peak time of the shaper, effectively eliminating the dead time caused by t_rst,pdh. Finally, the trigger signal from the time channel is utilized as a control signal, creating an event-driven analog memory. In this configuration, the PDH circuit exhibits minimal dead time for each detectable signal.

The proposed high-speed PDH circuit based on the aforementioned principles is illustrated in Fig. 8a. The circuit comprises two submodules, PDHA and PDHB, a control module, and a holding capacitor C_H. The PDHA and PDHB submodules employ peak-detection and holding circuits with a two-phase (read and write) configuration [30]. A folded cascade amplifier with a rail-to-rail input dynamic range is used in the PDH. The DC gain A₀ and DC common-mode rejection ratio (CMRR) and common-mode output reference $V_{\text{o,cm}}$ of the amplifier are optimized to improve the accuracy of the peak-height measurement of the PDH [31, 32]. PDHRST serves as an external reset signal, DIS represents the trigger signal from the time channel, and WA (WB), RA (RB), and RSTA (RSTB) denote the write, read, and reset signals for PDHA (PDHB), respectively. In addition, MODEL and SYN serve as the mode-control signals. In the case of MODEL=1, the PDHA and PDHB submodules collaborate, where the amplifier of PDHA serves as the write amplifier, and the amplifier of PDHB functions as a buffer (read amplifier), forming a continuous peak-detection and holding circuit [13]. The reset signal in this mode is supplied externally by the PDHRST, enabling the observation of the entire peak-sampling and holding process. This configuration is instrumental in testing the functionality and precision of the circuits. The experimental results indicate that the proposed PDH operates within an input-signal range of 10 mV to 2 V with a percentage error below 7% and nonlinearity error of less than 1%.

Fig. 8Full-screen View

(Color online) (a) Block diagram illustrating the peak-detection and holding circuit. (b) Simulation results of the peak-detection and holding circuit

When MODEL=0, the PDHA and PDHB submodules operate alternately and are controlled by a reset signal that transitions between their states. The reset signal is determined by the SYN signal, which provides the flexibility to select either an external input PDHRST (SYN=1) or the trigger signal DIS from the time channel (SYN=0). The simulation results for the high-speed PDH circuit with SYN=0 are shown in Fig. 8b. Each rising edge of the DIS signal corresponds to the arrival of an event, generating a control signal that triggers one submodule to enter the writing state (whereas the other enters the reading state). The submodule in the writing state has a 45 ns reset process, followed by the completion of peak sampling and the holding of the current event. Simultaneously, the submodule in the reading state reads out the held voltage from the previous event, and the duration of the reading state depends on when the next signal arrives, that is, the time interval between the two signals t_delay. The entire PDH circuit functions as an event-driven, first-in-first-out analog memory. If the input signal is detectable by the time channel, the PDH circuit can successfully capture and store the peak values of the shaper output signals. In this mode, the PDH circuit can detect piled-up signals from the shaper output, reducing the time interval between the input signals from 3.28t_p to 1.8t_p, resulting in an 82% increase in the count rate.