2.1. Architecture

High-resolution time and charge measurement are widely used in nuclear physics ^[10-12]. Fig. 1 shows a block diagram of the soft X-ray detection (SXD) readout electronics for time and energy measurement. It is mainly composed of two sections: analog and a digital electronics. In the analog electronics section, a pre-amplifier module (PA), a high voltage module(HV) and a temperature control module (TC) are specially designed by the Original Equipment Manufacturer of SDD. All the other modules after the PA are developed by our group. The PA output goes to two channels: the one marked as 'Q_out’ from a slow shaper is for energy measurement, and the other marked as 'T_out’ from a fast shaper is for time measurement.

Fig. 1Full-screen View

Block diagram of the SXD readout electronics.

In the digital electronics section, the 'Q_out’ is fed into an analog peak hold module, and then sampled by an analog-to-digital-converter (ADC), while the 'T_out’ is converted into a hit signal by a constant fraction timing circuit (CFT), and then sent to a time-to-digital-converter (TDC) for digitization. The ADC and TDC signals are buffered and fed into a data processor (DP). The system can be monitored and controlled by the DP according to the standard Controller Area Network (CAN) protocol. The external power supplies of the whole electronics are ±6 V, +5 V and +12 V.

2.2. Pre-amplifier

As shown in Fig. 2, a matched PA ^[13] for SDD is used to amplify the output current pulse of the detector, which offers an ultra-low noise, and a ramped reset type CSA with high gain (4.5 mV/keV ±15%). The amplitude of the ramped output signal is between ± 2 V with a reset duration of <5 µs, and the period of the reset ranges from a few milliseconds to a few hundred milliseconds, which depends on the frequency of the incoming photons and the temperature of the detector.

Fig. 2Full-screen View

Block diagram of PA connecting with SDD.

The output of PA is a voltage step when the signal produced by an X-ray photon appears. The rise time (from 10 ns to 100 ns ^[14]) mainly depends on the location where X-rays interact with the SDD, while the voltage amplitude depends on the energy deposition of the incoming photon.

2. 3.Energy measurement circuit

For energy measurement, the signal amplitude is detected efficiently, achieved via the analog peak detection and ADC method. As shown in Fig. 3, the PA is followed by a slow shaping circuit consisting of a CR-RC² filter, which is employed to form a quasi-Gaussian signal. The peak value of the quasi-Gaussian signal is held by a peak hold module (PH300 from Amp-Tek) and then digitalized by a 14-bit ADC (AD9243) with 3 MHz sampling clock. The pole zero cancellation circuit is not necessary in case that being the signal form PA a step voltage ^[15].

Fig.3Full-screen View

Block diagram of the energy measurement circuit.

Noise contribution of the SDD and readout electronics is analyzed, to find the performance-limiting factor of the system.

Energy resolution of the detector, staged in the datasheet, is 126.9 eV @ 5.9 keV ^[16] (at below −60°C using a Peltier cooler, peaking time of 16 µs). For the slow shaping circuit, a Pspice simulation shows that the noise RMS is 3.4 mV, which is equivalent to 44 eV @ 5.9 keV. A 14-bit ADC with a quantization error of 0.12 mV (1.5 eV @ 5.9 keV) is selected, which shall be a minor role in affecting the total energy resolution.

In addition, the rise time of the real signal will cause extra loss of the shaped signal height, which is termed as the Ballistic Deficit. Although increasing the peaking time (i.e. the time constant of CR and RC) can decrease the Ballistic Deficit, it will increase the dead time of the energy measurement. A peaking time of 2 µs is determined finally to guarantee a proper counting rate and the energy resolution. Test results with a signal generator show that the actual electronic noise (FWHM_electronic) of the energy measurement circuit is equivalent to 68 eV @ 5.9 keV as a constant in the dynamic range with a peaking time of 2 µs.

2.4. Time measurement circuit

Compared with leading edge timing, a constant fraction timing circuit essentially eliminates the amplitude-dependent time walk for signals and has better timing resolution ^[17]. Fig. 4 explains the CFT principle briefly, and a delay time '∆t’ of 8 ns as an attenuation coefficient 'q’ of 0.5 is chosen, leading to a fixed delay 't’ of 16 ns.

Fig. 4Full-screen View

A brief explanation of the CFT principle. The delay 't’ is constant and independent from the slope of the input signal.

As shown in Fig. 5, the PA is followed by a fast shaping circuit, which consists of an AC coupled circuit (CR with a time constant of 0.5 µs) and an amplifier, to condition the signals for time measurement. The fast shaper also drives three branches of the CFT circuits: the first branch is delayed by a time of 't_d’ (8 ns), the second one is attenuated by a coefficient of 'q’ (0.5) and the third one is compared with an adjustable threshold for noise canceling. The output of both comparators is fed into an 'AND’ gate for coincidence and then digitized by an FPGA based TDC.

Fig. 5Full-screen View

Block diagram of the time measurement circuit.

Since accuracy of time measurement is highly sensitive to CFT circuit, stringent hardware design is considered. A 100 Ω impedance fixed delay line (1919-20B, Data Delay Device) is used to achieve high precision delay and impedance matching. An ultra-high-speed comparator (MAX9601, MAXIM Inc.) is selected, with 30 ps propagation delay dispersion and differential PECL outputs. A programmable delay line (NB6L295 from ON semiconductor) configured at 5 ns, is used to delay the CFT branch to guarantee the timing constrain. The AND gate (MC100LVEL05,ON Semiconductor) has two differential ECL inputs with a propagation delay of 340 ps.

2.5. TDC integrated in FPGA

To digitize the output signals from the CFT module, a TDC is implemented in a XILINX FPGA (XC5VLX110), which reduces the system complexity and provides good flexibility ^{[18, 19]}. Fig. 6 shows its block diagram. The arrival time of the 'hit in’ signal is digitized by a 3-bit 'fine time’ and a 29-bit 'coarse counter’ modules, and then encoded to a final 32-bit time measurement result, which is finally read out by a FIFO.

Fig. 6Full-screen View

TDC integrated in the FPGA. 3-bit 'fine time’ and 29-bit 'coarse counter’ constitutes a final 32-bit time measurement result (with the bin size of 2.5 ns and dynamic range of 10.74 second).

A 50 MHz external clock is fed into the FPGA, and then used by an internal phase lock loop (PLL) to generate four 100 MHz clock outputs with 90° phase interval (0°, 90°, 180°, 270°), which is equivalent to 2.5 ns least significant bit (LSB) and much less than the transit time spread of SDD.

3.1. Energy measurement results

On the SXD system, using the ⁵⁵Fe source, the energy resolution is measured at 153.4 eV @ 5.9 keV FWHM (Fig. 7a). Statistical distribution of time intervals of two photons is shown in Fig. 7(b), where the counts have the characteristic of Poisson distribution and behave in accordance with the theoretical property of radioisotope.

Fig.7Full-screen View

Energy spectra (a) and time interval distribution (b) of a ⁵⁵Fe using the SXD system.

The energy resolution and linearity (properties of the detector and electronics) X-rays of different energies are listed in Table 1. The X-rays are electron beam-induced fluorescence from samples of Cu, Fe, Cr and Ti ^[20]. The linearity of one representative SDD indicates that the integral non-linearity (INL) of less than 0.1% can be achieved. It is worth noting that the minor INL can be corrected by off-line analysis.

3.2. Time measurement results

The RMS of time measurement is basically contributed by two factors: the noise of circuits and the quantization error. A 10 kHz pulse (30 ns rise time, 50 mV amplitude, generated by a Tektronix AFG3252) is utilized to drive the fast shaper module directly, to evaluate the performance of time measurement. Test results of the SXD (including contribution of both analog and digital electronics) are shown in Fig. 8. It can be seen that the standard deviation (STD) is 3.7 ns, which is much less than the transit time spread of SDD.

Fig. 8Full-screen View

Performance of time precision test with 10 kHz (period of 100 µs) pulse input.

As mentioned in Section 3.3, CFT essentially eliminates the amplitude-dependent time walk for signals. Fig. 9(a) shows the tests to observe performance of the CFT circuit. The first channel (CH1) is the reference signal with a frequency of 10 kHz and 2.5 ns rise time; while CH2 is created based on waveform of the fast shaper, which has different amplitude (0.4–4 V) with 10 ns rise time. Fig. 9(b) shows the performance of CFT circuit. The propagation delay of CFT circuit is 20 ns with the time walk less than 3 ns.

Fig. 9Full-screen View

Test method (a) and results (b) of the CFT circuit. Delay is the skew of the 'reference’ and the output of 'CFT’.