Framework and Principles of the Proposed TDC

Figure 1 shows the overall framework of the proposed TDC and the structure of a single channel. The PLL, DLLs and coarse counter are global for the chip, and 8 TDC channels with the same structure can operate independently. In actual applications with ROC, one TDC channel is used to sample the external start signal and the trigger signal generated by ROC, also called as the stop signal, is measured by another channel. The time interval between the start and stop, which is known as a timestamp, is calculated and stored off-chip.

Fig. 1Full-screen View

(Color online) The structure of the proposed 8-channel TDC

The reference clock of the chip, referred to as Clk, can be furnished by an integrated PLL or directly from the off-chip clock source. As shown in Fig. 1, DLL-1 and DLL-2 using Clk as the input clock are composed of delay lines with n and n-1 delay cells, respectively. The counter, as the first TDC level can be triggered by both the rising and falling edges of Clk. The results of the counter are delivered continuously to each TDC channel. The second TDC level is realized with multiphase clocks produced by DLL-1, which are fed to the clock sampler in each channel. The residual time of the second level, also known as the time interval between the hit event and its subsequent polyphase clock’s rising edge, is measured by the third TDC level – a VDL. The vernier measurement is carried out utilizing the slightly different delay-times between two delay cells τ₁ and τ₂, which are respectively controlled by DLL-1 and DLL-2. The resolution of TDC is determined by the third level, and is represented as given in (Eq. 2). (2)where f₀ denotes the frequency of Clk. The dynamic range of TDC is proportionate to the number of counter digits, which can be increased according to the limits of power consumption and die area [23]. We can use (Eq. 3) to signify the dynamic range of this TDC in which N₁ denotes the number of counter digits. (3)

Tradeoffs Among Key Parameters

From Eq. 2, it may be observed that the values of n and f₀ should be increased to obtain a finer resolution, which means that we should insert more delay cells in DLLs or use a reference clock of higher frequency. The precision of a TDC primarily involves two components, including quantizing and random noise. The former depends on the resolution, which can be obtained in the time domain as follows [13]. (4)The jitters generated from the reference clock, the hit signals, and those produced by DLLs likewise worsen the precision by contributing to random noise in the phase domain. Assuming that the clock and hit signals are as clean as expected, jitter mostly arises from DLLs. Figure 2a shows how the jitter from DLLs affects the precision of TDC. The hit signal is assumed to be located between and provided by DLL-1 such that a replica of is delivered to the VDL for the finest quantization. The jitter generated by a single delay cell is indicated as σ₀, owing to noise from the control voltage, power supply, and substrate. The jitter of is which is also the maximum accumulated jitter of DLL-1. As shown in Fig. 2b, the cycling occurs for m times on loops corresponding to Hit and , and OUTA and OUTB are output signals of VDL. Assuming that the jitters generated by the 4 cascaded delay cells in VDL are uncorrelated, the accumulated jitters on OUTA and OUTB are represented by Eq. 5 and Eq. 6, respectively. (5) (6)At the end of cycling, OUTA and OUTB are fed to an arbiter for phase comparison. Thus, the time uncertainty due to jitter can be regarded as the accumulation of σ_r1 and σ_r2 and is denoted as (7)whereas the value of m can be deduced with the relation between τ₁ and Re as (8)The total time uncertainty or time precision of TDC is represented as given below. (9)The proposed design includes a delay cell with symmetrical current-starved structure [24] as shown in Fig. 2c, which is characterized by almost equal rise and fall times. To avoid reversing the phase, the cell is composed of two current-starved inverters, the propagation delays of which are controlled by the output voltage of the DLL (VC1 or VC2). If we define the toggle point for both the rising and falling edges as , the unit propagation delay in DLL-1 can be obtained as (10)where C_L denotes the parasitic capacitance on the output node of each stage, I_CS denotes the mean value of the charging or discharging current through C_L during output level switching. According to [25], the phase noise of a delay cell is dominated by white noise, and the low-frequency noise can be neglected when the rising and falling edges are symmetric. Figure 2d shows the noise model of the delay cell considering a positive input step in which the noise contribution of PMOS is omitted. For simplicity, the bias transistors (NM2, PM2 in Fig. 2c) working in the triode region were replaced with resistors with negligible voltage drop. The input transistor (NM1 in Fig. 2d) is assumed to be saturated for simplification. Then the spectral density of output noise [26] can be described by (11)

Fig. 2Full-screen View

(Color online) (a) Jitter accumulations in the second level. (b) Jitter accumulations in the third level. (c)The simplified schematic of delay cell. (d) The noise model of delay cell

where is the threshold of NMOS and R_D denotes the value of the equivalent resistor of NM2 in Fig. 2c. As R_D can be considered a constant when the bias of NM2 is fixed, we adopted the phase-noise model for the inverter proposed in [27] to obtain the spectral density of the delay as given below. (12)where t_d is the statics of the random delay variable, which can be represented as (13)Then, the mean square value of t_d can be deduced using the Wiener–Khinchine theorem [27] as given below. (14)By applying Eqs. 10, 11, 12, and 13, this formula can be simplified to (15)On the assumption that the jitter produced with a negative input step is equivalent to that produced with a positive input step for a current-starved stage, the jitter of this delay cell with a positive input is represented by (16)Except for n and f₀, the terms in (Eq. 15) can be regarded as constants. f₀ is confined within (50 MHz, 100 MHz) with respect to power consumption. For simplicity, the resolution of TDC is set to a fixed value (e. g. 45 ps). The quantized jitter σ_q in formula (Eq. 4) is also fixed. Thus, we only need to reduce the random part of the jitter, which is derived as given in Eqs. 2, 7, 8, 15, and 16. (17)From (Eq. 17), we can understand that smaller values of n minimize the random jitter as much as possible. Given that Re is fixed at 45 ps, we determine that f₀=100 MHz and n=16. As a result, the ideal resolution of the proposed TDC is approximately 41.7 ps.

Delay-locked Loop

The structures of the two DLLs integrated into TDC are almost identical, as shown in Fig. 3a, except for the voltage-controlled delay lines (VCDLs) containing different numbers of delay cells. According to this analysis, the VCDLs in DLL-1 and DLL-2 contain 16 and 15 cells, respectively. A reference clock with a frequency of 100-MHz is fed to DLL-1 and DLL-2, which operate independently and do not need to be synchronized.

Fig. 3Full-screen View

(Color online) (a)The structure of DLL-1. (b) The implementation of symmetrical current-starved delay cell. (c) The delay-voltage characteristics of delay cell under different PVT conditions. (d) The effect of the control voltage shift on the TDC resolution

The lock controller [28] is used to prevent the DLL from false and harmonic locking events by comparing the first and several intermediate phases. The delay of VCDL is forced to range within 8 ns to 13.3 ns when the lock controller is enabled, which can also reduce the time required for the DLL to become locked. The phase detector operates in the first and last phases and determines the charging or discharging status of the charge pump. Complementary switches, dummy transistors, and a wide-swing cascaded current mirror are adopted in the charge pump to improve the degree of matching between charging and discharging to obtain a much smaller locked phase error. In addition, a start-up circuit is used to provide an appropriate initial value to VC1 and VC2.

The VCDL is composed of 15/16 cascaded delay cells and 2 dummy cells, all of which were based on a modified current-starved structure. As shown in Fig. 3b, variable PMOS resistances (PM2, PM5) and variable NMOS resistances (NM2, NM5) are controlled by V_BP and VC1 respectively, which vary in opposite directions. With appropriate transistor dimensions, we can obtain an output with approximately equal rising and falling times across the tuning range. However, the transistor NM0 used for biasing can contribute considerable noise, so that only one bias circuit is used in the DLL and the two control voltages, VC1 and V_BP, are shared by all the involved delay cells either in the VCDL or in TDC channels. The constant MOS resistances (PM3, PM6, NM3 and NM6) are employed to supply a basic working current and guarantee that the delay cell still operates when VC1 is lower than the threshold voltage of NMOS, which can prevent the DLL from being inactive.

Figure 3c shows the simulated delay-voltage characteristics under different PVT conditions. The effective tuning range of this delay cell is 390 ps to 850 ps, which covers the expected unit delays for both two DLLs (625 ps for DLL-1 and 666.7 ps for DLL-2). As the control voltages are transferred to multiple channels with separate distances from the DLLs, the control voltages shift variously at each channel. As shown in Fig. 3d, we suppose that the shifts of VC1 given by DLL-1 and VC2 given by DLL-2 are both ΔV. Given the high linearity of the delay-voltage characteristics within a small voltage range, the unit delays controlled by VC1 and VC2 are both skewed by Δt. Therefore, the resolutions of all the channels can be considered as roughly consistent, as they are dominated by the difference between these two unit delays.

First and Second Levels

The first TDC level is based on an 8-bit global counter with a double-edge-triggered structure [29] as shown in Fig. 4a. The counting results CntP and CntN obtained with the rising and falling edges of Clk respectively, are delivered to each channel simultaneously. The data selector in the channel is used to capture the proper counting result whenever the asynchronous Hit signal arrives, according to the result of the second level as shown in Fig. 4b. If the asynchronous input signal denoted by Hit is located in the first half of the clock cycle, we obtain and CntN is chosen as the result of the first level. In the case that the Hit occurs in the second half of the clock cycle, CntP is selected. The implementation of a double-edge-triggered counter and appropriate settings is designed to eliminate the metastability of the counter.

Fig. 4Full-screen View

(Color online) (a) Structure of double-edge-triggered counter. (b) Schematic of polyphase clock sampler and synchronizer. (c) The schematic of the modified VDL. (d) Timing diagram to illustrate the proposed automatic reset mechanism for VDL

One of the tasks of the second level is to measure the time interval between Hit and the first rising edge of Clk following the Hit, which can be realized using a polyphase clock sampler composed of 16 arbiters as shown in Fig. 4b. Another task is to transfer the residual time to the next level with the synchronizer. For example, if is captured by the sampler, the residual time is the time elapsed between Hit and . Although well-matched loads are inserted in both signal paths of the synchronizer, there are still errors between the input and output intervals. According to a Monte Carlo simulation, the maximum error was approximately 5.1 ps, which is considered tolerable because the final resolution is much larger than the error.

Third Level–Vernier Delay Loop

The VDL used to quantize the residual time of the second level is a modified version of that proposed in Ref. [18], as shown in Fig. 4c. The VDL contains 2 structurally identical loops. The loop with the input named SI₁ is a slow loop and that with the input named SI₂ is fast. SI₁ and SI₂ are the two outputs of synchronizer as shown in Fig. 4b. SI₁ precedes SI₂ and the interval between them is denoted by T_f varies within 0 ~ 625 ps. The edge-detection circuit is used to generate a narrow pulse when the rising edge of SI₁/SI₂ arrives. There are 2 types of unit delays in each loop τ₁ and τ₂, which are regulated by the control voltages provided by DLL-1 and DLL-2, respectively. The single-delay cell and arbiter are used to convert the narrow pulse into a pulse with a width of τ₂. The cycle periods are determined by the 3-cascaded delay cells in the scenario that the delays of other logic on the loop can be neglected, which are 3τ₂ for the slow loop and for the fast loop. As shown in Fig. 4c, signals at nodes A₁ and A₂ are denoted as SA₁ and SA₂, respectively. SA₁ precedes signal SA₂ by T_f before cycling, and the interval between SA₁ and SA₂ is decreased by after each cycle. The cycling stops when SA₂ catches up with SA₁. The number of cycles required to align SA₁ and SA₂ can be obtained using the pulse counter and represented as (18)

Ideally, the maximum n_f is 15, for which a 4-bit counter is sufficient. However, a redundant bit is added to calibrate the measurement results.

Because the VDL is expected to measure the arrival times of sequential pulses, an auxiliary circuit that can make VDL automatically reset after quantization is included as shown in the dotted box in Fig. 4c, where signals at nodes B, C, D and E are denoted as SB, SC, SD and SE, respectively. The timing diagram of the critical signals is shown in Fig. 4d. Before quantization, the global Rstn first takes SB to 0 to clear all nodes in the loop, and then SB is pulled up to 1 to obtain a loop ready for cycling. The cycling stage of VDL begins as soon as SI₁/SI₂ arrives. When SA₁ and SA₂ are aligned after several cycles, the flip-flop samples are set to 1, SB is set to 0, and both two loops are cleared. Synchronized with SB, SD and SE are successively pulled down to zero with a delay of 2τ₂. Subsequently, the flip-flop is cleared, and SB, SD, SE are pulled up to 1 in turn. After these steps, the VDL is once again ready for the next quantization. With this automatic reset mechanism, the maximum dead time of VDL is less than 45 ns, which implies that the conversion rate of a single channel can reach up to 22.5 MS/s. Considering the integration and serial readout of data from the 8 channels, the overall conversion rate of the proposed TDC chip can reach 5 MS/s. In addition to a fast ROC, the pileup effect in STCF EMC can be mitigated because the background counting rate is 1 MHz [7].

ASIC Prototype and Experiment Setups

The proposed 8-channel TDC was taped out using a standard 180 nm CMOS process with a 1.8 V power supply; a microphotograph of the chip is shown in Fig. 5a. The layout of TDC channel is designed with a strip shape, and 8 channels are arranged in a column, which makes VC1 and VC2’s distribution paths as short as possible. The chip has a die area of 1.55 mm × 1.42 mm, including the pad ring.

Fig. 5Full-screen View

(Color online) (a) The microphotograph of the proposed TDC chip. (b) The test system and PCB board for testing

Figure 5b shows the experimental setup composed of an oscilloscope to observe the signal series, a spectrum analyzer for jitter measurement, 2 pulse generators to provide the reference clock and input signals of TDC, an FPGA board, an upper computer for chip control, and a logic analyzer used to collect and process the measured data. We adopt a clock generator chip, AD9552, to provide a 100 MHz reference clock with a jitter below 1 ps, rms. The reference clock is directly given by pulse generator in linearity evaluation.

Performance of DLL

Three chips were tested and verified, which are referred to as chip-1, chip-2, and chip-3. Unless specifically indicated otherwise, all measurements described below were performed with chip-2. Two approaches were adopted to obtain the jitter of DLL. The firs was to obtain the phase noise curve of the last polyphase clock and integrate it within the frequency shift range of (10 KHz, 20 MHz), and the other was to measure the jitter directly with the oscilloscope. A jitter of 5 ps rms can be obtained using both approaches, which is much less than the resolution of TDC. The other performances are listed in Table 1.

Performance of TDC

For the first, we need to determine the actual resolution (LSB) of each TDC channel. Because the bin distributions are nearly consistent over all clock periods [29], we only need to evaluate the actual LSB within one clock period. One channel of the pulse generator is dedicated to providing the 100 MHz reference clock, and the TDC input with a frequency of 4.00001 MHz is derived from another channel. Thus, the interval between TDC input and the rising edge of the reference clock increases by 0.625 ps with each clock cycle. This interval is cyclically repeated within the range of 0 to 10 ns, which can be considered as an approximate method for code density testing [30].

In ideal scenarios, the number of bins within the 10 ns measurement range is fixed (approximately 240) with an LSB size of approximately 41.7 ps. However, many nonideal factors can cause the actual LSB to be either larger or smaller. The tested DNL and INL values of the second TDC level across 8 channels with high consistency are shown in Fig. 6a and Fig. 6b respectively. The nonlinearity of the second level mainly arose from mismatches of VCDL in DLL-1, which results in variable “margins” between the second and third levels. To explain this, we assume 2 types of step sizes for the second level with 600 ps and 650 ps, which are also intervals to be measured using VDL. Without considering nonideal factors in VDL, the resolution was fixed at 41.7 ps. Then, the sizes of VDL’s last VDL bins for the input intervals of 600 ps and 650 ps were set to 16.2 ps and 24.5 ps, respectively.

Fig. 6Full-screen View

(Color online) The test results of (a) DNL and (b) INL across 8 channels, only considering the second level.(The bin code on the x-axis also represents the interval between two adjacent multiphase clocks.) (c)The bin distribution of Ch-1 within a measuring range of 10-ns. (d)The actual LSBs of 8 channels across 3 chips

A bin-size filtration mechanism was implemented to prevent the last bin within the VDL quantization range from becoming too narrow to worsen the DNL. First, the approximate magnitude of LSB was ascertained. If the size of the last bin was less than LSB/4, it was combined the last bin with the second-to-last bin into a new bin. Otherwise, the final bin was retained. The bin distribution of Ch-1 within a single clock period is shown in Fig. 6c. The LSBs of eight channels after processing are presented in Fig. 6d, which shows the approximate measured results across 3 chips. The LSB of Ch-1 was larger than those of the other channels, which can be explained by the significant deviation in the supply voltage in this channel.

The distribution ranges of DNL and INL in each of the eight channels over a single clock period (10 ns) are listed in Table 2. We also assessed the linearity in the asynchronous measurement mode, in which Ch-1 served as the start channel and one of the other channels served as the stop channel. The code density test was performed again, in which Start and Stop were provided by a single pulse generator with frequencies of 4.00001 MHz and 4 MHz respectively. Because only the measurement results of the second and third levels are collected, the interval between the Start and Stop can be considered as randomly distributed within (0, 10 ns) with a 100 MHz reference clock. Table 3 shows the linearity performance of 7 channel combinations, from which it may be observed that DNLs better than 0.4 LSB and INLs better than 0.5 LSB were obtained for all test cases. Comparing the test results of the single- and dual-channel methods demonstrates that the asynchronous TDC inherently employing the sliding-scaled technique provides a great advantage in terms of linearity.

The single-shot precision (SSP) of the proposed TDC was measured in asynchronous mode. The output of the pulse generator was divided into two identical signals using a power splitter. One was transmitted to the start channel (Ch-1) through a 0.1 m cable, and the other was transmitted to the stop channel (one of the other channels) through a 0.3 m cable, which is referred to as a cable delay measurement test [29]. The best uncalibrated SSP of 52.4 ps was obtained using a combination of Ch-1 and Ch-2, as shown in Fig. 7a. The precision was improved by using the look-up table for INL [31]. The principle of calibration is expressed as follows. (19)where TDC_RAW and TDC_CAL denote the raw and calibrated TDC digits, respectively. The calibrated SSP for 46 ps is shown in Fig. 7b. The tested SSPs with other channel combinations are shown in Fig. 7c, which are all in the range of 45 ps to 70 ps after calibration.

Fig. 7Full-screen View

(Color online) (a) Uncalibrated SSP and (b) the calibrated SSP with the combination of Ch-1 and Ch-2. (c) SSP results across 7 channel combinations with cable delay measurement test. (d) SSP results along the range of (0.5-ns, 10-ns) with the combination of Ch-1 and Ch-2. (e) Tested accuracy along TDC’s dynamic range with the combination of Ch-1 and Ch-2. (f) Specification of two cases of correlated cross-talk between Start and Stop. (g) Measured SSP curve with time intervals within (0, 249-ns), which includes the two cases of correlated cross-talk

To validate the effectiveness of the calibration, we measured SSP along an input interval range of (0.5 ns, 10 ns). As shown in Fig. 7d, SSP results with different inputs become more consistent after calibration. As this calibration method relying on INL results is designed to compensate for nonuniform LSBs, the test results can mutually corroborate this theory. Hence, the test and calibration methods employed were proven to be correct. The accuracy represents the error between the input and output, which was also measured over the dynamic range of TDC as shown in Fig. 7e. Because the metastability was eliminated with the double-edge-triggered counter, no significant deviation in accuracy was observed in the test results.

The precision of TDC can be degraded due to the effect of cross-talk, which introduces distortion of the edges of the Start or Stop signals. Both correlated and uncorrelated cross-talk mechanisms can have an effect. Uncorrelated crosstalk is typically difficult to evaluate, and we focused more on correlated crosstalk [32]. An experiment was conducted to study the effects of the crosstalk. Two adjacent channels, Ch-1 and Ch-2, were used to obtain timestamps of the Start and Stop signals, respectively. The input pads of these two channels are close to each other so that the effect of crosstalk on them can be more significant. The Start and Stop signals were both 4 MHz, and the time intervals between them (denoted as T_m) varied within (0, 249 ns). As shown in Fig. 7f, the rising edges of the Start and Stop signals were distorted by each other with T_m = 0, and the rising edge of Stop will be distorted by the falling edges of Start with T_m = 125 ns. The SSP evaluations were performed at various time intervals. Although it may be observed from Fig. 7g that the SSP with T_m = 0 was significantly worse than other cases, it was not significant with the case of T_m = 125 ns. We speculate that this may be because the effect of crosstalk is greater when the rising edges of the Start and Stop are coincident. The effects of metastability can be neglected because of the asynchronous measurement mechanism and double-edge-triggered counter of this TDC, and the degradation of SSP can be explained by crosstalk. Therefore, these instances with correlated crosstalk should be excluded from the system’s operating mode of TDC.

Table 4 shows the comparison of the proposed TDC with others [33-39], which are all suitable for multichannel applications. Compared with the delay-line structure in Ref. [33] and the counter structure in Ref. [36], the proposed TDC has a notable advantage in terms of precision. These results show that our design exhibited superior conversion linearity in contrast to the structures based on ring oscillators given in Refs. [34] and [37]. The TDC proposed by Ref. [35] is also based on a vernier controlled with dual DLLs, but it exhibited worse linearity and a slower conversion rate compared to the proposed TDC [38] and [39] provide two TDCs based on Xilinx 7-series 28 nm FPGA, and the performance of our TDC was still competitive among them.