2.1. Preamplifier & discriminator circuits

The preamplifier and discriminator are implemented by the A111F hybrid chip. Due to the number of discrete anodes, 12 A111F chips are employed. Besides its high counting rate (~2.5 MHz) and low noise (0.44 fC for nominal threshold) performance, the A111F features a high sensitivity (8 fC), a 25 ns rise-time and a small size (occupying less space on the printed circuit board) [12]. And the discrimination threshold in the A111F is adjustable to filter non-interesting events. Although anode strips are connected to ground level via large resistors, a 1-nF high-voltage capacitor and a pair of clamping diodes are utilized at the input pin of A111F, to avoid possible high voltage discharge.

2.2. HV supply module

The HV supply module is designed to generate a sweeping HV and a fixed HV. Prior to event signals produced by the MCPs, a sweeping HV of −2300 V to −3.5 V is applied to the ESA, and a fixed HV at −2500 V~ −2300 V for biasing the MCPs. It includes a digital-to-analog converter (DAC), two amplifiers, a high voltage optocoupler, an HV module, an analog-to-digital converter (ADC) and some voltage-proof resistors, as shown in Fig. 3[13]. It generates a −3000 V output, which is divided by a resistor divider to get the fixed HV, meanwhile, is led to a fast HV optocoupler to generate the sweeping HV controlled by a DAC.

Fig. 3Full-screen View

The scheme of HV supply module.

2.3. Self-test circuitry

To check operating status of signal chains of the readout electronics in a complex and harsh space environment, a built-in self-test circuitry is utilized (Fig. 4). The DAC is controlled by an FPGA to output an adequate analog voltage. A narrow signal enables the analog switch to turn on, producing a test pulse to trigger A111Fs by capacitive coupling. Apart from checking the operating status, the data compress algorithm in FPGA can also be verified by accommodating the frequency of the test pulse.

Fig. 4Full-screen View

The simplified diagram of self-test circuitry.

2.4. Control and data processing unit

The control and data processing unit is implemented in FPGA (ACTEL Corp.). Its block diagram is shown in Fig. 5. In order to make the instrument into operative mode, related commands, sent by an upper computer and arriving at the subcell manage block after UART receiving and command parsing, are used to control or configure DACs, ADCs and other components orderly. When entering into counting mode, 12 counters (24-bit) record the event signals which are from A111Fs at the period of corresponding energy step for each channel. Then the 12 counting values at each energy step are accumulated cycle by cycle, respectively. After 64 cycles per spin, the last accumulated values of 24-bit raw data are compressed into 8-bit data by a log compression algorithm [14]. The decompression is given by Eq.(1), and the maximum loss rate is less than 8%. There is about 15K bit/s transmission rate without data compression, which surpasses considerably the 3.2K telemetry width. While counters are counting, the status of HV supply and low power operating current, and the ambient temperature, are collected. Under different working modes, the compressed event data, or the monitoring data, or both, is sent to the upper computer after data packing and framing.

Fig. 5Full-screen View

The block diagram of the control and data processing unit.

where, N is a raw 24 bit count datum, M is a 8 bit output code after compression, and N₁ is a datum after decompression.

Considering the dead time τ (<0.6×10⁻⁶s) of the signal chain, the true counting rate is then:

3.1. Electronics test

As shown in Fig.6(d), a signal generator (TEK AFG3252), together with a passive attenuator, outputs an appropriate negative pulse to preamplifiers in the electronics. The counting data are transferred to a remote PC for further analysis and display executed by a LabView program. An oscilloscope is used to measure the output signal for comparison. Against the background noise and crosstalk, an 184 fC threshold is configured for A111Fs. Under the condition of a 100 kHz narrow test signal, the input dynamic range expressed as the normalized threshold, is achieved by regulating the amplitude of input signal and the attenuation ratio. Fig.7 shows the counting rate verse the input charge, measured by both the readout electronics and the oscilloscope. There is a stable and flat count rates, about 98.3 kHz by the electronics and 100 kHz by the oscilloscope, in a wide input range from a 184 fC threshold to 95 pC (over 500 times of the threshold). For both ways of measurement, the counting rate drops sharply below the threshold of input, while it increases noticeably at input charges beyond 95 pC, which will be explained in Section 4.

Fig. 7Full-screen View

The input dynamic range.

With a suitable width-fixed test pulse generated by the built-in test circuit to trigger A111Fs, detection efficiency of the readout electronics at different event rates can be measured by adjusting the frequency of test signal which is accomplished by a self-test control unit in the FPGA via sending different control commands. The detection efficiencies at expected event rates are listed in Table 1, which verifies the log compression algorithm.

A linear sweeping test and a fixed voltage deviation test are conducted for the HV supply module, with a relative precision of < 0.8% for fixed HV, a 0.7% integral nonlinearity (Fig. 8), and a fast enough slew rate (0.8 V/μs) for the sweeping HV. More details can be found in Ref.[13].

Fig. 8Full-screen View

Correlation between tested step values and ideal step values.

3.2. Beam tests

A beam test system under ground-based vacuum facility is constructed to simulate the vacuum environment in space, as shown in Fig.9. The ion source injects a 2.5 keV Ar⁺ beam into the vacuum chamber, which covers the whole effective area of the sensor aperture. With the MCPs biased at −2500 V, the ESA is controlled to sweep in −150 V ~ −400 V to select the incident Ar⁺ beams.

Fig. 9Full-screen View

Diagram of the beam test system. The sensor lies on a stage in the vacuum chamber, while the readout electronics is outside.

Fig.10(a) shows the energy response represented by the counting rates of relevant channels. The energy resolution (ΔE/E) is 12% ±0.7% (FWHM) for Channel 8 by a Gaussian fitting (dashed curve). Fig.10(b) shows the baseline noise measurement with the ESA sweeping from −100 V to −800 V for Ch7 to Ch9. The noise counts is less than 10/sec.

Fig. 10Full-screen View

The energy response (a) and noise level (b) from Ch7 to Ch9.

4.1. Input dynamic range and double pulsing effect

Test results confirm that the readout electronics reaches an input dynamic range from 184 fC to 95 pC, as the counting rate is flat and accords with the compression algorithm which can be verified by a built-in circuit generating test pulses up to 1 MHz. The increase in counting rate with input charges beyond 95 pC is due to the double pulsing, which was also observed by lliev Metodi et al. [15].The double pulsing is yielded by the shape variation which creates the possibility that under the large input signals, the discriminator threshold may be crossed more than once during the duration of the pulse.

4.2. Energy resolution

In the Ar⁺ beam test, sizeable flux of Ar⁺ beams is injected into Ch8 and the counting rate of each channel is compared. The noise counting under different sweeping HV can manifest that the spectrometer is of low noise, since the count rate fits comfortably with the dark counts of MCP [16]. Due to the optimized ion optics design of the ESA and a low noise level, an energy resolution ΔE/E of 12% ±0.7% (FWHM) is achieved, which is better than the design specification of 15%.

4.3. Consideration for radiation mitigation

Because of the radiation environment in space, hazards can be imposed to the readout electronics. For example, TID can affect input bias current, offset voltage, transistor parameters, timing margins and so on for microcircuits, while SEEs can upset the logic state, cause malfunctions or even latch-up [17]. Apart from shielding, components with high TID tolerance have a higher priority during this electronics design. For example, A111F and LM6142 (operational amplifier) have a TID resistance over 100kRad (Si). There are also other measures to mitigate SEEs, such as adding current-limiting resistors to the input and power-supply pins of a component to reduce latch-up currents, using triple module redundancy (TMR) and parity check techniques for FPGA logic [18]. Some anti-fuse and Flash FPGA are much more suitable for aerospace applications because their logic elements are immune to SEE. For example, Actel ProASIC PLUS series Flash-based FPGAs are tolerant to single event upset (SEU), and their linear energy transfer (LET) threshold for single event latch-up (SEL) is over 104 (MeV-cm2/mg) [19]. However, in this prototype design, considering the cost and practical requirements, some commercial components including an FPGA are used instead of high-reliable ones. The detailed design of radiation mitigation and verification test will be a focus in the future version.